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Commit 67dea3c7 authored by Huacai Chen's avatar Huacai Chen Committed by Greg Kroah-Hartman
Browse files

MIPS/tlbex: Fix LDDIR usage in setup_pw() for Loongson-3 



commit d191aaffe3687d1e73e644c185f5f0550ec242b5 upstream.

LDDIR/LDPTE is Loongson-3's acceleration for Page Table Walking. If BD
(Base Directory, the 4th page directory) is not enabled, then GDOffset
is biased by BadVAddr[63:62]. So, if GDOffset (aka. BadVAddr[47:36] for
Loongson-3) is big enough, "0b11(BadVAddr[63:62])|BadVAddr[47:36]|...."
can far beyond pg_swapper_dir. This means the pg_swapper_dir may NOT be
accessed by LDDIR correctly, so fix it by set PWDirExt in CP0_PWCtl.

Cc: <stable@vger.kernel.org>
Signed-off-by: default avatarPei Huang <huangpei@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 76b48e98

arch/mips/mm/tlbex.c

+4 −1
Original line number Diff line number Diff line
@@ -1479,6 +1479,7 @@ static void build_r4000_tlb_refill_handler(void) 


static void setup_pw(void)

{

	unsigned int pwctl;

	unsigned long pgd_i, pgd_w;

#ifndef __PAGETABLE_PMD_FOLDED

	unsigned long pmd_i, pmd_w;
@@ -1505,6 +1506,7 @@ static void setup_pw(void) 


	pte_i = ilog2(_PAGE_GLOBAL);

	pte_w = 0;

	pwctl = 1 << 30; /* Set PWDirExt */



#ifndef __PAGETABLE_PMD_FOLDED

	write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i);
@@ -1515,8 +1517,9 @@ static void setup_pw(void) 
#endif



#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT

	write_c0_pwctl(1 << 6 | psn);

	pwctl |= (1 << 6 | psn);

#endif

	write_c0_pwctl(pwctl);

	write_c0_kpgd((long)swapper_pg_dir);

	kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */

}