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Commit 67bf63c2 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "arm64: Use the clearbhb instruction in mitigations"

parents 9bf24a89 1a6c401c

arch/arm64/include/asm/assembler.h

+7 −0
Original line number Diff line number Diff line
@@ -140,6 +140,13 @@ 
	hint	#20

	.endm



/*

 * Clear Branch History instruction

 */

	.macro clearbhb

	hint	#22

	.endm



/*

 * Sanitise a 64-bit bounded index wrt speculation, returning zero if out

 * of bounds.

arch/arm64/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ struct cpuinfo_arm64 { 
	u64		reg_id_aa64dfr1;

	u64		reg_id_aa64isar0;

	u64		reg_id_aa64isar1;

	u64		reg_id_aa64isar2;

	u64		reg_id_aa64mmfr0;

	u64		reg_id_aa64mmfr1;

	u64		reg_id_aa64mmfr2;

arch/arm64/include/asm/cpufeature.h

+13 −0
Original line number Diff line number Diff line
@@ -497,6 +497,19 @@ static inline bool supports_csv2p3(int scope) 
	return csv2_val == 3;

}



static inline bool supports_clearbhb(int scope)

{

	u64 isar2;



	if (scope == SCOPE_LOCAL_CPU)

		isar2 = read_sysreg_s(SYS_ID_AA64ISAR2_EL1);

	else

		isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);



	return cpuid_feature_extract_unsigned_field(isar2,

						    ID_AA64ISAR2_CLEARBHB_SHIFT);

}



static inline bool system_supports_32bit_el0(void)

{

	return cpus_have_const_cap(ARM64_HAS_32BIT_EL0);

arch/arm64/include/asm/sysreg.h

+4 −0
Original line number Diff line number Diff line
@@ -171,6 +171,7 @@ 


#define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)

#define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)

#define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)



#define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)

#define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
@@ -536,6 +537,9 @@ 
#define ID_AA64ISAR1_JSCVT_SHIFT	12

#define ID_AA64ISAR1_DPB_SHIFT		0



/* id_aa64isar2 */

#define ID_AA64ISAR2_CLEARBHB_SHIFT	28



/* id_aa64pfr0 */

#define ID_AA64PFR0_CSV3_SHIFT		60

#define ID_AA64PFR0_CSV2_SHIFT		56

arch/arm64/include/asm/vectors.h

+7 −0
Original line number Diff line number Diff line
@@ -33,6 +33,12 @@ enum arm64_bp_harden_el1_vectors { 
	 * canonical vectors.

	 */

	EL1_VECTOR_BHB_FW,



	/*

	 * Use the ClearBHB instruction, before branching to the canonical

	 * vectors.

	 */

	EL1_VECTOR_BHB_CLEAR_INSN,

#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */



	/*
@@ -44,6 +50,7 @@ enum arm64_bp_harden_el1_vectors { 
#ifndef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY

#define EL1_VECTOR_BHB_LOOP		-1

#define EL1_VECTOR_BHB_FW		-1

#define EL1_VECTOR_BHB_CLEAR_INSN	-1

#endif /* !CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */



/* The vectors to use on return from EL0. e.g. to remap the kernel */