Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 67a3e8fe authored by Ross Zwisler's avatar Ross Zwisler Committed by Dan Williams
Browse files

nd_blk: change aperture mapping from WC to WB

This should result in a pretty sizeable performance gain for reads.  For
rough comparison I did some simple read testing using PMEM to compare
reads of write combining (WC) mappings vs write-back (WB).  This was
done on a random lab machine.

PMEM reads from a write combining mapping:
	# dd of=/dev/null if=/dev/pmem0 bs=4096 count=100000
	100000+0 records in
	100000+0 records out
	409600000 bytes (410 MB) copied, 9.2855 s, 44.1 MB/s

PMEM reads from a write-back mapping:
	# dd of=/dev/null if=/dev/pmem0 bs=4096 count=1000000
	1000000+0 records in
	1000000+0 records out
	4096000000 bytes (4.1 GB) copied, 3.44034 s, 1.2 GB/s

To be able to safely support a write-back aperture I needed to add
support for the "read flush" _DSM flag, as outlined in the DSM spec:

http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf



This flag tells the ND BLK driver that it needs to flush the cache lines
associated with the aperture after the aperture is moved but before any
new data is read.  This ensures that any stale cache lines from the
previous contents of the aperture will be discarded from the processor
cache, and the new data will be read properly from the DIMM.  We know
that the cache lines are clean and will be discarded without any
writeback because either a) the previous aperture operation was a read,
and we never modified the contents of the aperture, or b) the previous
aperture operation was a write and we must have written back the dirtied
contents of the aperture to the DIMM before the I/O was completed.

In order to add support for the "read flush" flag I needed to add a
generic routine to invalidate cache lines, mmio_flush_range().  This is
protected by the ARCH_HAS_MMIO_FLUSH Kconfig variable, and is currently
only supported on x86.

Signed-off-by: default avatarRoss Zwisler <ross.zwisler@linux.intel.com>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent e2e05394
Loading
Loading
Loading
Loading
+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ config X86
	select ARCH_HAS_FAST_MULTIPLIER
	select ARCH_HAS_GCOV_PROFILE_ALL
	select ARCH_HAS_PMEM_API
	select ARCH_HAS_MMIO_FLUSH
	select ARCH_HAS_SG_CHAIN
	select ARCH_HAVE_NMI_SAFE_CMPXCHG
	select ARCH_MIGHT_HAVE_ACPI_PDC		if ACPI
+2 −0
Original line number Diff line number Diff line
@@ -89,6 +89,8 @@ int set_pages_rw(struct page *page, int numpages);

void clflush_cache_range(void *addr, unsigned int size);

#define mmio_flush_range(addr, size) clflush_cache_range(addr, size)

#ifdef CONFIG_DEBUG_RODATA
void mark_rodata_ro(void);
extern const int rodata_test_data;
+0 −2
Original line number Diff line number Diff line
@@ -248,8 +248,6 @@ static inline void flush_write_buffers(void)
#endif
}

#define ARCH_MEMREMAP_PMEM MEMREMAP_WB

#endif /* __KERNEL__ */

extern void native_io_delay(void);
+2 −0
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@
#include <asm/cpufeature.h>
#include <asm/special_insns.h>

#define ARCH_MEMREMAP_PMEM MEMREMAP_WB

#ifdef CONFIG_ARCH_HAS_PMEM_API
/**
 * arch_memcpy_to_pmem - copy data to persistent memory
+1 −0
Original line number Diff line number Diff line
@@ -410,6 +410,7 @@ config ACPI_NFIT
	tristate "ACPI NVDIMM Firmware Interface Table (NFIT)"
	depends on PHYS_ADDR_T_64BIT
	depends on BLK_DEV
	depends on ARCH_HAS_MMIO_FLUSH
	select LIBNVDIMM
	help
	  Infrastructure to probe ACPI 6 compliant platforms for
Loading