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Commit 6744842d authored by Camera Software Integration's avatar Camera Software Integration Committed by Gerrit - the friendly Code Review server
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Merge "msm: camera: isp: Create debugfs for STATs DMI and cfg dump" into camera-kernel.lnx.1.0

parents fd47adca 8169d423

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175_130.h

+174 −0
Original line number Diff line number Diff line
@@ -176,6 +176,179 @@ struct cam_vfe_top_ver2_reg_offset_module_ctrl zoom_175_130_reg = { 
	.enable   = 0x0000004C,

};



static struct cam_vfe_bus_ver2_stats_cfg_info stats_175_130_info  = {

	.dmi_offset_info = {

		.auto_increment = 0x00000100,

		.cfg_offset     = 0x00000C24,

		.addr_offset    = 0x00000C28,

		.data_hi_offset = 0x00000C2C,

		.data_lo_offset = 0x00000C30,

	},

	.stats_cfg_offset = {

		/* CAM_VFE_BUS_VER2_VFE_OUT_RDI0 */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_RDI1 */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_RDI2 */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_RDI3 */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_FULL */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_DS4 */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_DS16 */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_RAW_DUMP */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_FD */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_PDAF */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE */

		{

			.res_index      = CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE,

			.cfg_offset     = 0x00000AB8,

			.num_cfg        = 0x00000ABC,

			.cfg_size       = 0x00000AC0,

			.is_lut         = 0,

			.lut            = {

				.size           = -1,

				.bank_0         = -1,

				.bank_1         = -1,

			},

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST */

		{

			.res_index      =

				CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST,

			.cfg_offset     = 0x00000AD4,

			.num_cfg        = 0x00000AD8,

			.cfg_size       = 0x00000000,

			.is_lut         = 1,

			.lut            = {

				.size           = 180,

				.bank_0         = 0x36,

				.bank_1         = 0x37,

			},

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_STATS_TL_BG */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF */

		{

			.res_index      = CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF,

			.cfg_offset     = 0x00000AE4,

			.num_cfg        = 0x00000000,

			.cfg_size       = 0x00000000,

			.is_lut         = 1,

			.lut            = {

				.size           = 180,

				.bank_0         = 0x40,

				.bank_1         = 0x41,

			},

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_STATS_AWB_BG */

		{

			.res_index      = CAM_VFE_BUS_VER2_VFE_OUT_STATS_AWB_BG,

			.cfg_offset     = 0x00000BC8,

			.num_cfg        = 0x00000BCC,

			.cfg_size       = 0x00000BD0,

			.is_lut         = 0,

			.lut            = {

				.size           = -1,

				.bank_0         = -1,

				.bank_1         = -1,

			},

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST */

		{

			.res_index      = CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST,

			.cfg_offset     = 0x00000BE4,

			.num_cfg        = 0x00000BE8,

			.cfg_size       = 0x00000000,

			.is_lut         = 1,

			.lut            = {

				.size           = 180,

				.bank_0         = 0x3A,

				.bank_1         = -1,

			},

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_STATS_RS */

		{

			.res_index      = CAM_VFE_BUS_VER2_VFE_OUT_STATS_RS,

			.cfg_offset     = 0x00000BEC,

			.num_cfg        = 0x00000BF0,

			.cfg_size       = 0x00000BF4,

			.is_lut         = 0,

			.lut            = {

				.size           = -1,

				.bank_0         = -1,

				.bank_1         = -1,

			},

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_STATS_CS */

		{

			.res_index      = CAM_VFE_BUS_VER2_VFE_OUT_STATS_CS,

			.cfg_offset     = 0x00000BF8,

			.num_cfg        = 0x00000BFC,

			.cfg_size       = 0x00000C00,

			.is_lut         = 0,

			.lut            = {

				.size           = -1,

				.bank_0         = -1,

				.bank_1         = -1,

			},

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_STATS_IHIST */

		{

			.res_index      = CAM_VFE_BUS_VER2_VFE_OUT_STATS_IHIST,

			.cfg_offset     = 0x00000C04,

			.num_cfg        = 0x00000C08,

			.cfg_size       = 0x00000000,

			.is_lut         = 1,

			.lut            = {

				.size           = 180,

				.bank_0         = 0x3B,

				.bank_1         = 0x3C,

			},

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_FULL_DISP */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_DS4_DISP */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_DS16_DISP */

		{

		},

		/* CAM_VFE_BUS_VER2_VFE_OUT_2PD */

		{

			.res_index      = CAM_VFE_BUS_VER2_VFE_OUT_2PD,

			.cfg_offset     = 0x00000FF0,

			.num_cfg        = 0x00000FF4,

			.cfg_size       = 0x00000FF8,

			.is_lut         = 1,

			.lut            = {

				.size           = 180,

				.bank_0         = 0x44,

				.bank_1         = 0x45,

			},

		},

	},

};





static struct cam_vfe_top_ver2_reg_offset_common vfe175_130_top_common_reg = {

	.hw_version               = 0x00000000,

	.hw_capability            = 0x00000004,
@@ -1125,6 +1298,7 @@ static struct cam_vfe_bus_ver2_hw_info vfe175_130_bus_hw_info = { 
			.max_height    = 1080,

		},

	},

	.stats_data = &stats_175_130_info,

};



struct cam_vfe_hw_info cam_vfe175_130_hw_info = {

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c

+180 −15
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ static const char drv_name[] = "vfe_bus"; 
#define CAM_VFE_BUS_IRQ_REG2                     2

#define CAM_VFE_BUS_IRQ_MAX                      3



#define CAM_VFE_BUS_LUT_WORD_SIZE_64             1



#define CAM_VFE_BUS_VER2_PAYLOAD_MAX             256



#define CAM_VFE_BUS_SET_DEBUG_REG                0x82
@@ -100,6 +102,7 @@ struct cam_vfe_bus_ver2_common_data { 
	uint32_t                                    addr_no_sync;

	cam_hw_mgr_event_cb_func                    event_cb;

	bool                                        hw_init;

	struct cam_vfe_bus_ver2_stats_cfg_info     *stats_data;

};



struct cam_vfe_bus_ver2_wm_resource_data {
@@ -1366,6 +1369,40 @@ static int cam_vfe_bus_handle_wm_done_bottom_half(void *handler_priv, 
	return rc;

}



static void cam_vfe_bus_dump_dmi_reg(

	void __iomem    *mem_base,

	uint32_t        lut_word_size,

	uint32_t        lut_size,

	uint32_t        lut_bank_sel,

	struct cam_vfe_bus_ver2_dmi_offset_common dmi_cfg)

{

	uint32_t        i;

	uint32_t        val_0;

	uint32_t        val_1;



	val_0 = dmi_cfg.auto_increment | lut_bank_sel;

	cam_io_w_mb(val_0, mem_base + dmi_cfg.cfg_offset);

	cam_io_w_mb(0, mem_base + dmi_cfg.addr_offset);

	for (i = 0; i < lut_size; i++) {

		if (lut_word_size == CAM_VFE_BUS_LUT_WORD_SIZE_64) {

			val_0 = cam_io_r_mb(mem_base +

				dmi_cfg.data_lo_offset);

			val_1 = cam_io_r_mb(mem_base +

				dmi_cfg.data_hi_offset);

			CAM_INFO(CAM_ISP,

				"Bank%d : 0x%x, LO: 0x%x, HI:0x%x",

				lut_bank_sel, i, val_0, val_1);

		} else {

			val_0 = cam_io_r_mb(mem_base +

				dmi_cfg.data_lo_offset);

			CAM_INFO(CAM_ISP, "Bank%d : 0x%x, LO: 0x%x",

				lut_bank_sel, i, val_0);

		}

	}

	cam_io_w_mb(0, mem_base + dmi_cfg.cfg_offset);

	cam_io_w_mb(0, mem_base + dmi_cfg.addr_offset);

}





static int cam_vfe_bus_err_bottom_half(void *handler_priv,

	void *evt_payload_priv)
@@ -1374,6 +1411,8 @@ static int cam_vfe_bus_err_bottom_half(void *handler_priv, 
	struct cam_vfe_bus_ver2_priv *bus_priv = handler_priv;

	struct cam_vfe_bus_ver2_common_data *common_data;

	struct cam_isp_hw_event_info evt_info;

	struct cam_vfe_bus_ver2_stats_cfg_offset *stats_cfg;

	struct cam_vfe_bus_ver2_dmi_offset_common dmi_cfg;

	uint32_t val = 0;



	if (!handler_priv || !evt_payload_priv)
@@ -1382,6 +1421,8 @@ static int cam_vfe_bus_err_bottom_half(void *handler_priv, 
	evt_payload = evt_payload_priv;

	common_data = &bus_priv->common_data;



	stats_cfg = common_data->stats_data->stats_cfg_offset;

	dmi_cfg = common_data->stats_data->dmi_offset_info;

	val = evt_payload->debug_status_0;

	CAM_ERR(CAM_ISP, "Bus Violation: debug_status_0 = 0x%x", val);
@@ -1415,35 +1456,158 @@ static int cam_vfe_bus_err_bottom_half(void *handler_priv, 
	if (val & 0x0200)

		CAM_INFO(CAM_ISP, "RAW DUMP violation");



	if (val & 0x0400)

	if (val & 0x0400) {

		CAM_INFO(CAM_ISP, "PDAF violation");

		cam_vfe_bus_dump_dmi_reg(common_data->mem_base,

			CAM_VFE_BUS_LUT_WORD_SIZE_64,

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_PDAF].lut.size,

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_PDAF].lut.bank_0,

			dmi_cfg);

		CAM_INFO(CAM_ISP, "RGN offset cfg 0x%08x",



		cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_PDAF].cfg_offset));

	}



	if (val & 0x0800) {

		CAM_INFO(CAM_ISP, "STATs HDR BE vltn RGN offset cfg 0x%08x",

			cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE].cfg_offset));



	if (val & 0x0800)

		CAM_INFO(CAM_ISP, "STATs HDR BE violation");

		CAM_INFO(CAM_ISP, "RGN num cfg 0x%08x",

			cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE].num_cfg));

	}



	if (val & 0x01000)

	if (val & 0x01000) {

		CAM_INFO(CAM_ISP, "STATs HDR BHIST violation");

		cam_vfe_bus_dump_dmi_reg(common_data->mem_base,

			CAM_VFE_BUS_LUT_WORD_SIZE_64,

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST].lut.size,

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST].lut.bank_0,

			dmi_cfg);



		cam_vfe_bus_dump_dmi_reg(common_data->mem_base,

			CAM_VFE_BUS_LUT_WORD_SIZE_64,

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST].lut.size,

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST].lut.bank_1,

			dmi_cfg);



		CAM_INFO(CAM_ISP, "RGN offset cfg 0x%08x",

		cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST].cfg_offset));



		CAM_INFO(CAM_ISP, "RGN num cfg 0x%08x",

		cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST].num_cfg));

	}



	if (val & 0x02000)

		CAM_INFO(CAM_ISP, "STATs TINTLESS BG violation");



	if (val & 0x04000)

	if (val & 0x04000) {

		CAM_INFO(CAM_ISP, "STATs BF violation");

		cam_vfe_bus_dump_dmi_reg(common_data->mem_base,

			CAM_VFE_BUS_LUT_WORD_SIZE_64,

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF].lut.size,

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF].lut.bank_0,

			dmi_cfg);



		cam_vfe_bus_dump_dmi_reg(common_data->mem_base,

			CAM_VFE_BUS_LUT_WORD_SIZE_64,

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF].lut.size,

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF].lut.bank_1,

			dmi_cfg);



		CAM_INFO(CAM_ISP, "RGN offset cfg 0x%08x",

		cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF].cfg_offset));

	}



	if (val & 0x08000) {

		CAM_INFO(CAM_ISP, "STATs AWB BG UBWC vltn RGN ofst cfg 0x%08x",

		cam_io_r_mb(common_data->mem_base +

		stats_cfg[

		CAM_VFE_BUS_VER2_VFE_OUT_STATS_AWB_BG].cfg_offset));



		CAM_INFO(CAM_ISP, "RGN num cfg 0x%08x",

		cam_io_r_mb(common_data->mem_base +

		stats_cfg[

		CAM_VFE_BUS_VER2_VFE_OUT_STATS_AWB_BG].num_cfg));

	}



	if (val & 0x010000) {

		CAM_INFO(CAM_ISP, "STATs BHIST violation");

		cam_vfe_bus_dump_dmi_reg(common_data->mem_base,

			CAM_VFE_BUS_LUT_WORD_SIZE_64,

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST].lut.size,

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST].lut.bank_0,

			dmi_cfg);



	if (val & 0x08000)

		CAM_INFO(CAM_ISP, "STATs AWB BG UBWC violation");

		CAM_INFO(CAM_ISP, "RGN offset cfg 0x%08x",

		cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST].cfg_offset));



	if (val & 0x010000)

		CAM_INFO(CAM_ISP, "STATs BHIST violation");

		CAM_INFO(CAM_ISP, "RGN num cfg 0x%08x",

		cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST].num_cfg));

	}



	if (val & 0x020000)

		CAM_INFO(CAM_ISP, "STATs RS violation");

	if (val & 0x020000) {

		CAM_INFO(CAM_ISP, "STATs RS violation RGN offset cfg 0x%08x",

			cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_RS].cfg_offset));



	if (val & 0x040000)

		CAM_INFO(CAM_ISP, "STATs CS violation");

		CAM_INFO(CAM_ISP, "RGN num cfg 0x%08x",

		cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_RS].num_cfg));

	}



	if (val & 0x080000)

		CAM_INFO(CAM_ISP, "STATs IHIST violation");

	if (val & 0x040000) {

		CAM_INFO(CAM_ISP, "STATs CS violation RGN offset cfg 0x%08x",

		cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_CS].cfg_offset));



		CAM_INFO(CAM_ISP, "RGN num cfg 0x%08x",

		cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_CS].num_cfg));

	}



	if (val & 0x080000) {

		CAM_INFO(CAM_ISP, "STATs IHIST vltn RGN offset cfg 0x%08x",

		cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_IHIST].cfg_offset));



		CAM_INFO(CAM_ISP, "RGN num cfg 0x%08x",

		cam_io_r_mb(common_data->mem_base +

			stats_cfg[

			CAM_VFE_BUS_VER2_VFE_OUT_STATS_IHIST].num_cfg));

	}



	if (val & 0x0100000)

		CAM_INFO(CAM_ISP, "DISP Y 1:1 UBWC violation");
@@ -3634,6 +3798,7 @@ int cam_vfe_bus_ver2_init( 
	bus_priv->common_data.addr_no_sync       =

		CAM_VFE_BUS_ADDR_NO_SYNC_DEFAULT_VAL;

	bus_priv->common_data.hw_init            = false;

	bus_priv->common_data.stats_data         = ver2_hw_info->stats_data;



	mutex_init(&bus_priv->common_data.bus_mutex);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.h

+46 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _CAM_VFE_BUS_VER2_H_
@@ -61,6 +61,36 @@ enum cam_vfe_bus_ver2_vfe_out_type { 
	CAM_VFE_BUS_VER2_VFE_OUT_MAX,

};



struct cam_vfe_bus_ver2_dmi_lut_bank_info {

	uint32_t size;

	uint32_t bank_0;

	uint32_t bank_1;

};



struct cam_vfe_bus_ver2_stats_cfg_offset {

	uint32_t res_index;

	uint32_t cfg_offset;

	uint32_t num_cfg;

	uint32_t cfg_size;

	uint32_t is_lut;

	struct cam_vfe_bus_ver2_dmi_lut_bank_info lut;

};



struct cam_vfe_bus_ver2_dmi_offset_common {

	uint32_t auto_increment;

	uint32_t cfg_offset;

	uint32_t addr_offset;

	uint32_t data_hi_offset;

	uint32_t data_lo_offset;

};



struct cam_vfe_bus_ver2_stats_cfg_info {

	struct cam_vfe_bus_ver2_dmi_offset_common

		dmi_offset_info;

	struct cam_vfe_bus_ver2_stats_cfg_offset

		stats_cfg_offset[CAM_VFE_BUS_VER2_VFE_OUT_MAX];

};



/*

 * struct cam_vfe_bus_ver2_reg_offset_common:

 *
@@ -168,6 +198,19 @@ struct cam_vfe_bus_ver2_vfe_out_hw_info { 
	uint32_t                            max_height;

};



/*

 * struct cam_vfe_bus_ver2_reg_data:

 *

 * @Brief:        Holds the bus register data

 */



struct cam_vfe_bus_ver2_reg_data {

	uint32_t      ubwc_10bit_threshold_lossy_0;

	uint32_t      ubwc_10bit_threshold_lossy_1;

	uint32_t      ubwc_8bit_threshold_lossy_0;

	uint32_t      ubwc_8bit_threshold_lossy_1;

};



/*

 * struct cam_vfe_bus_ver2_hw_info:

 *
@@ -188,6 +231,8 @@ struct cam_vfe_bus_ver2_hw_info { 
	uint32_t num_out;

	struct cam_vfe_bus_ver2_vfe_out_hw_info

		vfe_out_hw_info[CAM_VFE_BUS_VER2_VFE_OUT_MAX];

	struct cam_vfe_bus_ver2_reg_data  reg_data;

	struct cam_vfe_bus_ver2_stats_cfg_info *stats_data;

};



/*