Loading drivers/soc/qcom/dcc_v2.c +5 −0 Original line number Diff line number Diff line Loading @@ -719,6 +719,7 @@ static int dcc_enable(struct dcc_drvdata *drvdata) int ret = 0; int list; uint32_t ram_cfg_base; uint32_t hw_info; mutex_lock(&drvdata->mutex); Loading Loading @@ -754,6 +755,10 @@ static int dcc_enable(struct dcc_drvdata *drvdata) drvdata->ram_offset/4, DCC_FD_BASE(list)); dcc_writel(drvdata, 0xFFF, DCC_LL_TIMEOUT(list)); hw_info = dcc_readl(drvdata, DCC_HW_INFO); if (hw_info & 0x80) dcc_writel(drvdata, 0x3F, DCC_TRANS_TIMEOUT(list)); /* 4. Clears interrupt status register */ dcc_writel(drvdata, 0, DCC_LL_INT_ENABLE(list)); dcc_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)), Loading Loading
drivers/soc/qcom/dcc_v2.c +5 −0 Original line number Diff line number Diff line Loading @@ -719,6 +719,7 @@ static int dcc_enable(struct dcc_drvdata *drvdata) int ret = 0; int list; uint32_t ram_cfg_base; uint32_t hw_info; mutex_lock(&drvdata->mutex); Loading Loading @@ -754,6 +755,10 @@ static int dcc_enable(struct dcc_drvdata *drvdata) drvdata->ram_offset/4, DCC_FD_BASE(list)); dcc_writel(drvdata, 0xFFF, DCC_LL_TIMEOUT(list)); hw_info = dcc_readl(drvdata, DCC_HW_INFO); if (hw_info & 0x80) dcc_writel(drvdata, 0x3F, DCC_TRANS_TIMEOUT(list)); /* 4. Clears interrupt status register */ dcc_writel(drvdata, 0, DCC_LL_INT_ENABLE(list)); dcc_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)), Loading