Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 66d59b67 authored by Stefan Agner's avatar Stefan Agner Committed by Shawn Guo
Browse files

ARM: dts: imx7-colibri: add MCP2515 CAN controller 



The Colibri Evaluation Carrier Board provides a MCP2515 CAN
controller connected via SPI. Note that the i.MX 7 provides
an internal CAN controller which is much better suited for CAN
operations. Using the MCP2515 with a Colibri iMX7 module is
mainly useful to test the SPI interface.

Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 6deb2260

arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi

+25 −0
Original line number Diff line number Diff line
@@ -45,6 +45,13 @@ 
		stdout-path = "serial0:115200n8";

	};



	/* fixed crystal dedicated to mpc258x */

	clk16m: clk16m {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <16000000>;

	};



	panel: panel {

		compatible = "edt,et057090dhu";

		backlight = <&bl>;
@@ -99,6 +106,24 @@ 
	status = "okay";

};



&ecspi3 {

	status = "okay";



	mcp2515: can@0 {

		compatible = "microchip,mcp2515";

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_can_int>;

		reg = <0>;

		clocks = <&clk16m>;

		interrupt-parent = <&gpio5>;

		interrupts = <2 IRQ_TYPE_EDGE_FALLING>;

		spi-max-frequency = <10000000>;

		vdd-supply = <&reg_3v3>;

		xceiver-supply = <&reg_5v0>;

		status = "okay";

	};

};



&fec1 {

	status = "okay";

};

arch/arm/boot/dts/imx7-colibri.dtsi

+12 −1
Original line number Diff line number Diff line
@@ -92,6 +92,12 @@ 
	cpu-supply = <&reg_DCDC2>;

};



&ecspi3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;

	cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;

};



&fec1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet1>;
@@ -313,7 +319,6 @@ 
		fsl,pins = <

			MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3	0x74 /* SODIMM 55 */

			MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2	0x74 /* SODIMM 63 */

			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0X14 /* SODIMM 73 */

			MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16	0x14 /* SODIMM 77 */

			MX7D_PAD_EPDC_DATA09__GPIO2_IO9		0x14 /* SODIMM 89 */

			MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x74 /* SODIMM 91 */
@@ -400,6 +405,12 @@ 
		>;

	};



	pinctrl_can_int: can-int-grp {

		fsl,pins = <

			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0X14 /* SODIMM 73 */

		>;

	};



	pinctrl_enet1: enet1grp {

		fsl,pins = <

			MX7D_PAD_ENET1_CRS__GPIO7_IO14			0x14