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Commit 66c28d6d authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: patch the IBs for the second UVD instance v2 



Patch the IBs for the second UVD instance so that userspace don't need
to care about the instance they submit to.

v2: use direct IB patching

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-and-tested-by: default avatarJames Zhu <James.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9d248517

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

+29 −0
Original line number Diff line number Diff line
@@ -1205,6 +1205,34 @@ static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) 
	return r;

}



/**

 * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission.

 *

 * @p: the CS parser with the IBs

 * @ib_idx: which IB to patch

 *

 */

static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,

					   uint32_t ib_idx)

{

	struct amdgpu_ib *ib = &p->job->ibs[ib_idx];

	unsigned i;



	/* No patching necessary for the first instance */

	if (!p->ring->me)

		return 0;



	for (i = 0; i < ib->length_dw; i += 2) {

		uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);



		reg -= p->adev->reg_offset[UVD_HWIP][0][1];

		reg += p->adev->reg_offset[UVD_HWIP][1][1];



		amdgpu_set_ib_value(p, ib_idx, i, reg);

	}

	return 0;

}



/**

 * uvd_v7_0_ring_emit_ib - execute indirect buffer

 *
@@ -1697,6 +1725,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { 
	.get_rptr = uvd_v7_0_ring_get_rptr,

	.get_wptr = uvd_v7_0_ring_get_wptr,

	.set_wptr = uvd_v7_0_ring_set_wptr,

	.patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place,

	.emit_frame_size =

		6 + /* hdp invalidate */

		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +