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Commit 666cb873 authored by Thierry Reding's avatar Thierry Reding
Browse files

drm/tegra: dc: Unify enabling the display controller 



Previously output drivers would enable continuous display mode and power
up the display controller at various points during the initialization.
This is suboptimal because it accesses display controller registers in
output drivers and duplicates a bit of code.

Move this code into the display controller driver and enable the display
controller as the final step of the ->mode_set_nofb() implementation.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 8f604f8c

drivers/gpu/drm/tegra/dc.c

+12 −0
Original line number Original line Diff line number Diff line
@@ -1236,6 +1236,18 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc) 
		value &= ~INTERLACE_ENABLE;

		value &= ~INTERLACE_ENABLE;

		tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);

		tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);

	}

	}



	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);

	value &= ~DISP_CTRL_MODE_MASK;

	value |= DISP_CTRL_MODE_C_DISPLAY;

	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);



	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);

	value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |

		 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;

	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);



	tegra_dc_commit(dc);

}

}





static void tegra_crtc_prepare(struct drm_crtc *crtc)

static void tegra_crtc_prepare(struct drm_crtc *crtc)

drivers/gpu/drm/tegra/dsi.c

+0 −10
Original line number Original line Diff line number Diff line
@@ -824,16 +824,6 @@ static void tegra_dsi_encoder_mode_set(struct drm_encoder *encoder, 
	value |= DSI_ENABLE;

	value |= DSI_ENABLE;

	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);





	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);

	value &= ~DISP_CTRL_MODE_MASK;

	value |= DISP_CTRL_MODE_C_DISPLAY;

	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);



	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);

	value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |

		 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;

	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);



	tegra_dc_commit(dc);

	tegra_dc_commit(dc);





	/* enable DSI controller */

	/* enable DSI controller */

drivers/gpu/drm/tegra/hdmi.c

+0 −10
Original line number Original line Diff line number Diff line
@@ -1022,16 +1022,6 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder, 
	value |= HDMI_ENABLE;

	value |= HDMI_ENABLE;

	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);





	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);

	value &= ~DISP_CTRL_MODE_MASK;

	value |= DISP_CTRL_MODE_C_DISPLAY;

	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);



	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);

	value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |

		 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;

	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);



	tegra_dc_commit(dc);

	tegra_dc_commit(dc);





	/* TODO: add HDCP support */

	/* TODO: add HDCP support */

drivers/gpu/drm/tegra/rgb.c

+1 −10
Original line number Original line Diff line number Diff line
@@ -168,16 +168,6 @@ static void tegra_rgb_encoder_mode_set(struct drm_encoder *encoder, 
	value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;

	value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;

	tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);

	tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);





	value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_COMMAND);

	value &= ~DISP_CTRL_MODE_MASK;

	value |= DISP_CTRL_MODE_C_DISPLAY;

	tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_COMMAND);



	value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL);

	value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |

		 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;

	tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_POWER_CONTROL);



	tegra_dc_commit(rgb->dc);

	tegra_dc_commit(rgb->dc);





	if (output->panel)

	if (output->panel)
@@ -193,6 +183,7 @@ static void tegra_rgb_encoder_disable(struct drm_encoder *encoder) 
		drm_panel_disable(output->panel);

		drm_panel_disable(output->panel);





	tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));

	tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));

	tegra_dc_commit(rgb->dc);





	if (output->panel)

	if (output->panel)

		drm_panel_unprepare(output->panel);

		drm_panel_unprepare(output->panel);

drivers/gpu/drm/tegra/sor.c

+3 −22
Original line number Original line Diff line number Diff line
@@ -261,17 +261,8 @@ static int tegra_sor_attach(struct tegra_sor *sor) 




static int tegra_sor_wakeup(struct tegra_sor *sor)

static int tegra_sor_wakeup(struct tegra_sor *sor)

{

{

	struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);

	unsigned long value, timeout;

	unsigned long value, timeout;





	/* enable display controller outputs */

	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);

	value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |

		 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;

	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);



	tegra_dc_commit(dc);



	timeout = jiffies + msecs_to_jiffies(250);

	timeout = jiffies + msecs_to_jiffies(250);





	/* wait for head to wake up */

	/* wait for head to wake up */
@@ -1112,18 +1103,6 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder, 
		goto unlock;

		goto unlock;

	}

	}





	/* start display controller in continuous mode */

	value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);

	value |= WRITE_MUX;

	tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);



	tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);

	tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);



	value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);

	value &= ~WRITE_MUX;

	tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);



	/*

	/*

	 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete

	 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete

	 * raster, associate with display controller)

	 * raster, associate with display controller)
@@ -1198,11 +1177,13 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder, 
		goto unlock;

		goto unlock;

	}

	}





	tegra_sor_update(sor);



	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);

	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);

	value |= SOR_ENABLE;

	value |= SOR_ENABLE;

	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);





	tegra_sor_update(sor);

	tegra_dc_commit(dc);





	err = tegra_sor_attach(sor);

	err = tegra_sor_attach(sor);

	if (err < 0) {

	if (err < 0) {