disp: pll: fix divider clock flags for DSI PLL clocks

The divider clocks in the DSI PLL are 1-based and can accept
a value of 0. Set the flags accordingly in the PLL driver.

CRs-Fixed: 2433864
Change-Id: I82361ae3e2119f9e1922153bd5aba6354e8c5442
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>