Loading drivers/gpu/drm/msm/sde/sde_hw_catalog.c +10 −3 Original line number Diff line number Diff line Loading @@ -64,7 +64,8 @@ #define MAX_DOWNSCALE_RATIO 4 #define SSPP_UNITY_SCALE 1 #define MAX_DOWNSCALE_RATIO_INLINE_ROT_DEFAULT 2 #define MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DEFAULT 2 #define MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT 4 #define MAX_PRE_ROT_HEIGHT_INLINE_ROT_DEFAULT 1088 #define MAX_HORZ_DECIMATION 4 Loading Loading @@ -1104,8 +1105,10 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, if (IS_SDE_INLINE_ROT_REV_100(sde_cfg->true_inline_rot_rev)) { set_bit(SDE_SSPP_TRUE_INLINE_ROT_V1, &sspp->features); sblk->in_rot_format_list = sde_cfg->inline_rot_formats; sblk->in_rot_maxdwnscale = MAX_DOWNSCALE_RATIO_INLINE_ROT_DEFAULT; sblk->in_rot_maxdwnscale_rt = sde_cfg->true_inline_dwnscale_rt; sblk->in_rot_maxdwnscale_nrt = sde_cfg->true_inline_dwnscale_nrt; sblk->in_rot_maxheight = MAX_PRE_ROT_HEIGHT_INLINE_ROT_DEFAULT; } Loading Loading @@ -3598,6 +3601,10 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->has_hdr = true; sde_cfg->has_vig_p010 = true; sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0; sde_cfg->true_inline_dwnscale_rt = MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DEFAULT; sde_cfg->true_inline_dwnscale_nrt = MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT; } else { SDE_ERROR("unsupported chipset id:%X\n", hw_rev); sde_cfg->perf.min_prefill_lines = 0xffff; Loading drivers/gpu/drm/msm/sde/sde_hw_catalog.h +8 −2 Original line number Diff line number Diff line Loading @@ -556,7 +556,8 @@ struct sde_qos_lut_tbl { * @format_list: Pointer to list of supported formats * @virt_format_list: Pointer to list of supported formats for virtual planes * @in_rot_format_list: Pointer to list of supported formats for inline rotation * @in_rot_maxdwnscale: max downscale ratio for inline rotation * @in_rot_maxdwnscale_rt: max downscale ratio for inline rotation rt clients * @in_rot_maxdwnscale_nrt: max downscale ratio for inline rotation nrt clients * @in_rot_maxheight: max pre rotated height for inline rotation * @llcc_scid: scid for the system cache * @llcc_slice size: slice size of the system cache Loading Loading @@ -589,7 +590,8 @@ struct sde_sspp_sub_blks { const struct sde_format_extended *format_list; const struct sde_format_extended *virt_format_list; const struct sde_format_extended *in_rot_format_list; u32 in_rot_maxdwnscale; u32 in_rot_maxdwnscale_rt; u32 in_rot_maxdwnscale_nrt; u32 in_rot_maxheight; int llcc_scid; size_t llcc_slice_size; Loading Loading @@ -1078,6 +1080,8 @@ struct sde_perf_cfg { * @vbif_qos_nlvl number of vbif QoS priority level * @ts_prefill_rev prefill traffic shaper feature revision * @true_inline_rot_rev inline rotator feature revision * @true_inline_dwnscale_rt true inline rotator downscale ratio for rt * @true_inline_dwnscale_nrt true inline rotator downscale ratio for nrt * @macrotile_mode UBWC parameter for macro tile channel distribution * @pipe_order_type indicate if it is required to specify pipe order * @delay_prg_fetch_start indicates if throttling the fetch start is required Loading Loading @@ -1128,6 +1132,8 @@ struct sde_mdss_cfg { u32 vbif_qos_nlvl; u32 ts_prefill_rev; u32 true_inline_rot_rev; u32 true_inline_dwnscale_rt; u32 true_inline_dwnscale_nrt; u32 macrotile_mode; u32 pipe_order_type; bool delay_prg_fetch_start; Loading drivers/gpu/drm/msm/sde/sde_plane.c +38 −9 Original line number Diff line number Diff line Loading @@ -1625,14 +1625,17 @@ static int sde_plane_rot_atomic_check(struct drm_plane *plane, struct msm_drm_private *priv = plane->dev->dev_private; struct sde_kms *sde_kms; if (!psde->pipe_sblk->in_rot_maxdwnscale || if (!psde->pipe_sblk->in_rot_maxdwnscale_rt || !psde->pipe_sblk->in_rot_maxdwnscale_nrt || !psde->pipe_sblk->in_rot_maxheight || !psde->pipe_sblk->in_rot_format_list || !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT_V1))) { SDE_ERROR_PLANE(psde, "invalid rot config max:%d fmt:%d feat:0x%x\n", !psde->pipe_sblk->in_rot_maxdwnscale, "wrong config rt:%d nrt:%d fmt:%d h:%d 0x%x\n", !psde->pipe_sblk->in_rot_maxdwnscale_rt, !psde->pipe_sblk->in_rot_maxdwnscale_nrt, !psde->pipe_sblk->in_rot_format_list, !psde->pipe_sblk->in_rot_maxheight, psde->features); ret = -EINVAL; goto exit; Loading Loading @@ -2444,10 +2447,14 @@ static int sde_plane_sspp_atomic_check(struct drm_plane *plane, rt_client = true; /* inline rotation RT clients have a different max downscaling limit */ if (inline_rotation && rt_client) max_downscale = psde->pipe_sblk->in_rot_maxdwnscale; if (inline_rotation) { if (rt_client) max_downscale = psde->pipe_sblk->in_rot_maxdwnscale_rt; else max_downscale = psde->pipe_sblk->in_rot_maxdwnscale_nrt; } else { max_downscale = psde->pipe_sblk->maxdwnscale; } SDE_DEBUG_PLANE(psde, "check %d -> %d\n", sde_plane_enabled(plane->state), sde_plane_enabled(state)); Loading Loading @@ -3375,6 +3382,13 @@ static void _sde_plane_install_properties(struct drm_plane *plane, const struct sde_format_extended *inline_rot_fmt_list; sde_kms_info_add_keyint(info, "true_inline_rot_rev", 1); sde_kms_info_add_keyint(info, "true_inline_dwnscale_rt", psde->pipe_sblk->in_rot_maxdwnscale_rt); sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt", psde->pipe_sblk->in_rot_maxdwnscale_nrt); sde_kms_info_add_keyint(info, "true_inline_max_height", psde->pipe_sblk->in_rot_maxheight); inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list; if (inline_rot_fmt_list) { Loading Loading @@ -4092,6 +4106,21 @@ static int _sde_plane_init_debugfs(struct drm_plane *plane) psde->debugfs_root, &psde->debugfs_default_scale); if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT_V1)) { debugfs_create_u32("in_rot_max_downscale_rt", 0600, psde->debugfs_root, (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt); debugfs_create_u32("in_rot_max_downscale_nrt", 0600, psde->debugfs_root, (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt); debugfs_create_u32("in_rot_max_height", 0600, psde->debugfs_root, (u32 *) &psde->pipe_sblk->in_rot_maxheight); } debugfs_create_u32("xin_id", 0400, psde->debugfs_root, Loading Loading
drivers/gpu/drm/msm/sde/sde_hw_catalog.c +10 −3 Original line number Diff line number Diff line Loading @@ -64,7 +64,8 @@ #define MAX_DOWNSCALE_RATIO 4 #define SSPP_UNITY_SCALE 1 #define MAX_DOWNSCALE_RATIO_INLINE_ROT_DEFAULT 2 #define MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DEFAULT 2 #define MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT 4 #define MAX_PRE_ROT_HEIGHT_INLINE_ROT_DEFAULT 1088 #define MAX_HORZ_DECIMATION 4 Loading Loading @@ -1104,8 +1105,10 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, if (IS_SDE_INLINE_ROT_REV_100(sde_cfg->true_inline_rot_rev)) { set_bit(SDE_SSPP_TRUE_INLINE_ROT_V1, &sspp->features); sblk->in_rot_format_list = sde_cfg->inline_rot_formats; sblk->in_rot_maxdwnscale = MAX_DOWNSCALE_RATIO_INLINE_ROT_DEFAULT; sblk->in_rot_maxdwnscale_rt = sde_cfg->true_inline_dwnscale_rt; sblk->in_rot_maxdwnscale_nrt = sde_cfg->true_inline_dwnscale_nrt; sblk->in_rot_maxheight = MAX_PRE_ROT_HEIGHT_INLINE_ROT_DEFAULT; } Loading Loading @@ -3598,6 +3601,10 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->has_hdr = true; sde_cfg->has_vig_p010 = true; sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0; sde_cfg->true_inline_dwnscale_rt = MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DEFAULT; sde_cfg->true_inline_dwnscale_nrt = MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT; } else { SDE_ERROR("unsupported chipset id:%X\n", hw_rev); sde_cfg->perf.min_prefill_lines = 0xffff; Loading
drivers/gpu/drm/msm/sde/sde_hw_catalog.h +8 −2 Original line number Diff line number Diff line Loading @@ -556,7 +556,8 @@ struct sde_qos_lut_tbl { * @format_list: Pointer to list of supported formats * @virt_format_list: Pointer to list of supported formats for virtual planes * @in_rot_format_list: Pointer to list of supported formats for inline rotation * @in_rot_maxdwnscale: max downscale ratio for inline rotation * @in_rot_maxdwnscale_rt: max downscale ratio for inline rotation rt clients * @in_rot_maxdwnscale_nrt: max downscale ratio for inline rotation nrt clients * @in_rot_maxheight: max pre rotated height for inline rotation * @llcc_scid: scid for the system cache * @llcc_slice size: slice size of the system cache Loading Loading @@ -589,7 +590,8 @@ struct sde_sspp_sub_blks { const struct sde_format_extended *format_list; const struct sde_format_extended *virt_format_list; const struct sde_format_extended *in_rot_format_list; u32 in_rot_maxdwnscale; u32 in_rot_maxdwnscale_rt; u32 in_rot_maxdwnscale_nrt; u32 in_rot_maxheight; int llcc_scid; size_t llcc_slice_size; Loading Loading @@ -1078,6 +1080,8 @@ struct sde_perf_cfg { * @vbif_qos_nlvl number of vbif QoS priority level * @ts_prefill_rev prefill traffic shaper feature revision * @true_inline_rot_rev inline rotator feature revision * @true_inline_dwnscale_rt true inline rotator downscale ratio for rt * @true_inline_dwnscale_nrt true inline rotator downscale ratio for nrt * @macrotile_mode UBWC parameter for macro tile channel distribution * @pipe_order_type indicate if it is required to specify pipe order * @delay_prg_fetch_start indicates if throttling the fetch start is required Loading Loading @@ -1128,6 +1132,8 @@ struct sde_mdss_cfg { u32 vbif_qos_nlvl; u32 ts_prefill_rev; u32 true_inline_rot_rev; u32 true_inline_dwnscale_rt; u32 true_inline_dwnscale_nrt; u32 macrotile_mode; u32 pipe_order_type; bool delay_prg_fetch_start; Loading
drivers/gpu/drm/msm/sde/sde_plane.c +38 −9 Original line number Diff line number Diff line Loading @@ -1625,14 +1625,17 @@ static int sde_plane_rot_atomic_check(struct drm_plane *plane, struct msm_drm_private *priv = plane->dev->dev_private; struct sde_kms *sde_kms; if (!psde->pipe_sblk->in_rot_maxdwnscale || if (!psde->pipe_sblk->in_rot_maxdwnscale_rt || !psde->pipe_sblk->in_rot_maxdwnscale_nrt || !psde->pipe_sblk->in_rot_maxheight || !psde->pipe_sblk->in_rot_format_list || !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT_V1))) { SDE_ERROR_PLANE(psde, "invalid rot config max:%d fmt:%d feat:0x%x\n", !psde->pipe_sblk->in_rot_maxdwnscale, "wrong config rt:%d nrt:%d fmt:%d h:%d 0x%x\n", !psde->pipe_sblk->in_rot_maxdwnscale_rt, !psde->pipe_sblk->in_rot_maxdwnscale_nrt, !psde->pipe_sblk->in_rot_format_list, !psde->pipe_sblk->in_rot_maxheight, psde->features); ret = -EINVAL; goto exit; Loading Loading @@ -2444,10 +2447,14 @@ static int sde_plane_sspp_atomic_check(struct drm_plane *plane, rt_client = true; /* inline rotation RT clients have a different max downscaling limit */ if (inline_rotation && rt_client) max_downscale = psde->pipe_sblk->in_rot_maxdwnscale; if (inline_rotation) { if (rt_client) max_downscale = psde->pipe_sblk->in_rot_maxdwnscale_rt; else max_downscale = psde->pipe_sblk->in_rot_maxdwnscale_nrt; } else { max_downscale = psde->pipe_sblk->maxdwnscale; } SDE_DEBUG_PLANE(psde, "check %d -> %d\n", sde_plane_enabled(plane->state), sde_plane_enabled(state)); Loading Loading @@ -3375,6 +3382,13 @@ static void _sde_plane_install_properties(struct drm_plane *plane, const struct sde_format_extended *inline_rot_fmt_list; sde_kms_info_add_keyint(info, "true_inline_rot_rev", 1); sde_kms_info_add_keyint(info, "true_inline_dwnscale_rt", psde->pipe_sblk->in_rot_maxdwnscale_rt); sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt", psde->pipe_sblk->in_rot_maxdwnscale_nrt); sde_kms_info_add_keyint(info, "true_inline_max_height", psde->pipe_sblk->in_rot_maxheight); inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list; if (inline_rot_fmt_list) { Loading Loading @@ -4092,6 +4106,21 @@ static int _sde_plane_init_debugfs(struct drm_plane *plane) psde->debugfs_root, &psde->debugfs_default_scale); if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT_V1)) { debugfs_create_u32("in_rot_max_downscale_rt", 0600, psde->debugfs_root, (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt); debugfs_create_u32("in_rot_max_downscale_nrt", 0600, psde->debugfs_root, (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt); debugfs_create_u32("in_rot_max_height", 0600, psde->debugfs_root, (u32 *) &psde->pipe_sblk->in_rot_maxheight); } debugfs_create_u32("xin_id", 0400, psde->debugfs_root, Loading