Loading drivers/i3c/master/i3c-master-qcom-geni.c +16 −2 Original line number Diff line number Diff line Loading @@ -117,6 +117,7 @@ enum i3c_trans_dir { struct geni_se { void __iomem *base; void __iomem *ibi_base; struct device *dev; struct se_geni_rsc i3c_rsc; }; Loading Loading @@ -299,6 +300,7 @@ static void qcom_geni_i3c_conf(struct geni_i3c_dev *gi3c) writel_relaxed(val, gi3c->se.base + SE_GENI_HW_IRQ_CMD_PARAM_0); writel_relaxed(1, gi3c->se.base + SE_GENI_HW_IRQ_EN); geni_write_reg(1, gi3c->se.ibi_base, 0x2C); } static void geni_i3c_err(struct geni_i3c_dev *gi3c, int err) Loading Loading @@ -598,7 +600,8 @@ static void geni_i3c_perform_daa(struct geni_i3c_dev *gi3c) dev_dbg(gi3c->se.dev, "i3c entdaa read\n"); xfer.m_cmd = I2C_READ; xfer.m_param = STOP_STRETCH | CONTINUOUS_MODE_DAA | USE_7E; xfer.m_param = STOP_STRETCH | CONTINUOUS_MODE_DAA | USE_7E | IBI_NACK_TBL_CTRL; ret = i3c_geni_execute_read_command(gi3c, &xfer, rx_buf, 8); if (ret) Loading Loading @@ -644,7 +647,8 @@ static void geni_i3c_perform_daa(struct geni_i3c_dev *gi3c) dev_dbg(gi3c->se.dev, "i3c entdaa write\n"); xfer.m_cmd = I2C_WRITE; xfer.m_param = STOP_STRETCH | BYPASS_ADDR_PHASE | USE_7E; xfer.m_param = STOP_STRETCH | BYPASS_ADDR_PHASE | USE_7E | IBI_NACK_TBL_CTRL; ret = i3c_geni_execute_write_command(gi3c, &xfer, tx_buf, 1); if (ret) Loading Loading @@ -1113,6 +1117,7 @@ static int i3c_geni_rsrcs_init(struct geni_i3c_dev *gi3c, struct device_node *wrapper_ph_node; int ret; /* base register address */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -EINVAL; Loading @@ -1121,6 +1126,15 @@ static int i3c_geni_rsrcs_init(struct geni_i3c_dev *gi3c, if (IS_ERR(gi3c->se.base)) return PTR_ERR(gi3c->se.base); /* IBI register address */ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (!res) return -EINVAL; gi3c->se.ibi_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(gi3c->se.ibi_base)) return PTR_ERR(gi3c->se.ibi_base); wrapper_ph_node = of_parse_phandle(pdev->dev.of_node, "qcom,wrapper-core", 0); if (IS_ERR_OR_NULL(wrapper_ph_node)) { Loading drivers/platform/msm/qcom-geni-se.c +3 −0 Original line number Diff line number Diff line Loading @@ -338,6 +338,9 @@ static int geni_se_select_fifo_mode(void __iomem *base) geni_write_reg(common_geni_m_irq_en, base, SE_GENI_M_IRQ_EN); geni_write_reg(common_geni_s_irq_en, base, SE_GENI_S_IRQ_EN); geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN); if (proto == I3C) geni_write_reg(0x3, base, GENI_I3C_IBI_LEGACY); return 0; } Loading include/linux/qcom-geni-se.h +5 −0 Original line number Diff line number Diff line Loading @@ -116,6 +116,7 @@ struct se_geni_rsc { #define SE_GENI_IOS (0x908) #define SE_GENI_M_GP_LENGTH (0x910) #define SE_GENI_S_GP_LENGTH (0x914) #define GENI_I3C_IBI_LEGACY (0xA9c) #define SE_GSI_EVENT_EN (0xE18) #define SE_IRQ_EN (0xE1C) #define SE_HW_PARAM_0 (0xE24) Loading Loading @@ -259,6 +260,10 @@ struct se_geni_rsc { #define GENI_M_EVENT_EN (BIT(2)) #define GENI_S_EVENT_EN (BIT(3)) /* GENI_I3C_IBI_LEGACY fields */ #define I3C_IBI_LEGACY_EN (BIT(0)) #define I3C_IBI_LEGACY_PORTS_EN (BIT(1)) /* SE_GENI_IOS fields */ #define IO2_DATA_IN (BIT(1)) #define RX_DATA_IN (BIT(0)) Loading Loading
drivers/i3c/master/i3c-master-qcom-geni.c +16 −2 Original line number Diff line number Diff line Loading @@ -117,6 +117,7 @@ enum i3c_trans_dir { struct geni_se { void __iomem *base; void __iomem *ibi_base; struct device *dev; struct se_geni_rsc i3c_rsc; }; Loading Loading @@ -299,6 +300,7 @@ static void qcom_geni_i3c_conf(struct geni_i3c_dev *gi3c) writel_relaxed(val, gi3c->se.base + SE_GENI_HW_IRQ_CMD_PARAM_0); writel_relaxed(1, gi3c->se.base + SE_GENI_HW_IRQ_EN); geni_write_reg(1, gi3c->se.ibi_base, 0x2C); } static void geni_i3c_err(struct geni_i3c_dev *gi3c, int err) Loading Loading @@ -598,7 +600,8 @@ static void geni_i3c_perform_daa(struct geni_i3c_dev *gi3c) dev_dbg(gi3c->se.dev, "i3c entdaa read\n"); xfer.m_cmd = I2C_READ; xfer.m_param = STOP_STRETCH | CONTINUOUS_MODE_DAA | USE_7E; xfer.m_param = STOP_STRETCH | CONTINUOUS_MODE_DAA | USE_7E | IBI_NACK_TBL_CTRL; ret = i3c_geni_execute_read_command(gi3c, &xfer, rx_buf, 8); if (ret) Loading Loading @@ -644,7 +647,8 @@ static void geni_i3c_perform_daa(struct geni_i3c_dev *gi3c) dev_dbg(gi3c->se.dev, "i3c entdaa write\n"); xfer.m_cmd = I2C_WRITE; xfer.m_param = STOP_STRETCH | BYPASS_ADDR_PHASE | USE_7E; xfer.m_param = STOP_STRETCH | BYPASS_ADDR_PHASE | USE_7E | IBI_NACK_TBL_CTRL; ret = i3c_geni_execute_write_command(gi3c, &xfer, tx_buf, 1); if (ret) Loading Loading @@ -1113,6 +1117,7 @@ static int i3c_geni_rsrcs_init(struct geni_i3c_dev *gi3c, struct device_node *wrapper_ph_node; int ret; /* base register address */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -EINVAL; Loading @@ -1121,6 +1126,15 @@ static int i3c_geni_rsrcs_init(struct geni_i3c_dev *gi3c, if (IS_ERR(gi3c->se.base)) return PTR_ERR(gi3c->se.base); /* IBI register address */ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (!res) return -EINVAL; gi3c->se.ibi_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(gi3c->se.ibi_base)) return PTR_ERR(gi3c->se.ibi_base); wrapper_ph_node = of_parse_phandle(pdev->dev.of_node, "qcom,wrapper-core", 0); if (IS_ERR_OR_NULL(wrapper_ph_node)) { Loading
drivers/platform/msm/qcom-geni-se.c +3 −0 Original line number Diff line number Diff line Loading @@ -338,6 +338,9 @@ static int geni_se_select_fifo_mode(void __iomem *base) geni_write_reg(common_geni_m_irq_en, base, SE_GENI_M_IRQ_EN); geni_write_reg(common_geni_s_irq_en, base, SE_GENI_S_IRQ_EN); geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN); if (proto == I3C) geni_write_reg(0x3, base, GENI_I3C_IBI_LEGACY); return 0; } Loading
include/linux/qcom-geni-se.h +5 −0 Original line number Diff line number Diff line Loading @@ -116,6 +116,7 @@ struct se_geni_rsc { #define SE_GENI_IOS (0x908) #define SE_GENI_M_GP_LENGTH (0x910) #define SE_GENI_S_GP_LENGTH (0x914) #define GENI_I3C_IBI_LEGACY (0xA9c) #define SE_GSI_EVENT_EN (0xE18) #define SE_IRQ_EN (0xE1C) #define SE_HW_PARAM_0 (0xE24) Loading Loading @@ -259,6 +260,10 @@ struct se_geni_rsc { #define GENI_M_EVENT_EN (BIT(2)) #define GENI_S_EVENT_EN (BIT(3)) /* GENI_I3C_IBI_LEGACY fields */ #define I3C_IBI_LEGACY_EN (BIT(0)) #define I3C_IBI_LEGACY_PORTS_EN (BIT(1)) /* SE_GENI_IOS fields */ #define IO2_DATA_IN (BIT(1)) #define RX_DATA_IN (BIT(0)) Loading