Loading arch/arm/mach-shmobile/Kconfig +2 −0 Original line number Diff line number Diff line Loading @@ -116,4 +116,6 @@ endmenu config SH_CLK_CPG bool source "drivers/sh/Kconfig" endif arch/arm/mach-shmobile/board-ap4evb.c +45 −1 Original line number Diff line number Diff line Loading @@ -565,12 +565,50 @@ static struct platform_device *qhd_devices[] __initdata = { /* FSI */ #define IRQ_FSI evt2irq(0x1840) static int fsi_set_rate(int is_porta, int rate) { struct clk *fsib_clk; struct clk *fdiv_clk = &sh7372_fsidivb_clk; int ret; /* set_rate is not needed if port A */ if (is_porta) return 0; fsib_clk = clk_get(NULL, "fsib_clk"); if (IS_ERR(fsib_clk)) return -EINVAL; switch (rate) { case 48000: clk_set_rate(fsib_clk, clk_round_rate(fsib_clk, 85428000)); clk_set_rate(fdiv_clk, clk_round_rate(fdiv_clk, 12204000)); ret = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64; break; default: pr_err("unsupported rate in FSI2 port B\n"); ret = -EINVAL; break; } clk_put(fsib_clk); return ret; } static struct sh_fsi_platform_info fsi_info = { .porta_flags = SH_FSI_BRS_INV | SH_FSI_OUT_SLAVE_MODE | SH_FSI_IN_SLAVE_MODE | SH_FSI_OFMT(PCM) | SH_FSI_IFMT(PCM), .portb_flags = SH_FSI_BRS_INV | SH_FSI_BRM_INV | SH_FSI_LRS_INV | SH_FSI_OFMT(SPDIF), .set_rate = fsi_set_rate, }; static struct resource fsi_resources[] = { Loading Loading @@ -634,6 +672,7 @@ static struct platform_device lcdc1_device = { static struct sh_mobile_hdmi_info hdmi_info = { .lcd_chan = &sh_mobile_lcdc1_info.ch[0], .lcd_dev = &lcdc1_device.dev, .flags = HDMI_SND_SRC_SPDIF, }; static struct resource hdmi_resources[] = { Loading Loading @@ -992,6 +1031,7 @@ static void __init ap4evb_map_io(void) #define GPIO_PORT9CR 0xE6051009 #define GPIO_PORT10CR 0xE605100A #define USCCR1 0xE6058144 static void __init ap4evb_init(void) { u32 srcr4; Loading Loading @@ -1062,7 +1102,7 @@ static void __init ap4evb_init(void) /* setup USB phy */ __raw_writew(0x8a0a, 0xE6058130); /* USBCR2 */ /* enable FSI2 */ /* enable FSI2 port A (ak4643) */ gpio_request(GPIO_FN_FSIAIBT, NULL); gpio_request(GPIO_FN_FSIAILR, NULL); gpio_request(GPIO_FN_FSIAISLD, NULL); Loading @@ -1079,6 +1119,10 @@ static void __init ap4evb_init(void) gpio_request(GPIO_PORT41, NULL); gpio_direction_input(GPIO_PORT41); /* setup FSI2 port B (HDMI) */ gpio_request(GPIO_FN_FSIBCK, NULL); __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ /* set SPU2 clock to 119.6 MHz */ clk = clk_get(NULL, "spu_clk"); if (!IS_ERR(clk)) { Loading arch/arm/mach-shmobile/clock-sh7372.c +102 −0 Original line number Diff line number Diff line Loading @@ -50,6 +50,9 @@ #define SMSTPCR3 0xe615013c #define SMSTPCR4 0xe6150140 #define FSIDIVA 0xFE1F8000 #define FSIDIVB 0xFE1F8008 /* Platforms must set frequency on their DV_CLKI pin */ struct clk sh7372_dv_clki_clk = { }; Loading Loading @@ -288,6 +291,7 @@ struct clk sh7372_pllc2_clk = { .ops = &pllc2_clk_ops, .parent = &extal1_div2_clk, .freq_table = pllc2_freq_table, .nr_freqs = ARRAY_SIZE(pllc2_freq_table) - 1, .parent_table = pllc2_parent, .parent_num = ARRAY_SIZE(pllc2_parent), }; Loading Loading @@ -417,6 +421,101 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2), }; /* FSI DIV */ static unsigned long fsidiv_recalc(struct clk *clk) { unsigned long value; value = __raw_readl(clk->mapping->base); if ((value & 0x3) != 0x3) return 0; value >>= 16; if (value < 2) return 0; return clk->parent->rate / value; } static long fsidiv_round_rate(struct clk *clk, unsigned long rate) { return clk_rate_div_range_round(clk, 2, 0xffff, rate); } static void fsidiv_disable(struct clk *clk) { __raw_writel(0, clk->mapping->base); } static int fsidiv_enable(struct clk *clk) { unsigned long value; value = __raw_readl(clk->mapping->base) >> 16; if (value < 2) { fsidiv_disable(clk); return -ENOENT; } __raw_writel((value << 16) | 0x3, clk->mapping->base); return 0; } static int fsidiv_set_rate(struct clk *clk, unsigned long rate, int algo_id) { int idx; if (clk->parent->rate == rate) { fsidiv_disable(clk); return 0; } idx = (clk->parent->rate / rate) & 0xffff; if (idx < 2) return -ENOENT; __raw_writel(idx << 16, clk->mapping->base); return fsidiv_enable(clk); } static struct clk_ops fsidiv_clk_ops = { .recalc = fsidiv_recalc, .round_rate = fsidiv_round_rate, .set_rate = fsidiv_set_rate, .enable = fsidiv_enable, .disable = fsidiv_disable, }; static struct clk_mapping sh7372_fsidiva_clk_mapping = { .phys = FSIDIVA, .len = 8, }; struct clk sh7372_fsidiva_clk = { .ops = &fsidiv_clk_ops, .parent = &div6_reparent_clks[DIV6_FSIA], /* late install */ .mapping = &sh7372_fsidiva_clk_mapping, }; static struct clk_mapping sh7372_fsidivb_clk_mapping = { .phys = FSIDIVB, .len = 8, }; struct clk sh7372_fsidivb_clk = { .ops = &fsidiv_clk_ops, .parent = &div6_reparent_clks[DIV6_FSIB], /* late install */ .mapping = &sh7372_fsidivb_clk_mapping, }; static struct clk *late_main_clks[] = { &sh7372_fsidiva_clk, &sh7372_fsidivb_clk, }; enum { MSTP001, MSTP131, MSTP130, MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, Loading Loading @@ -585,6 +684,9 @@ void __init sh7372_clock_init(void) if (!ret) ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) ret = clk_register(late_main_clks[k]); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); if (!ret) Loading arch/arm/mach-shmobile/include/mach/gpio.h +2 −2 Original line number Diff line number Diff line Loading @@ -35,12 +35,12 @@ static inline int gpio_cansleep(unsigned gpio) static inline int gpio_to_irq(unsigned gpio) { return -ENOSYS; return __gpio_to_irq(gpio); } static inline int irq_to_gpio(unsigned int irq) { return -EINVAL; return -ENOSYS; } #endif /* CONFIG_GPIOLIB */ Loading arch/arm/mach-shmobile/include/mach/sh7372.h +2 −0 Original line number Diff line number Diff line Loading @@ -464,5 +464,7 @@ extern struct clk sh7372_dv_clki_div2_clk; extern struct clk sh7372_pllc2_clk; extern struct clk sh7372_fsiack_clk; extern struct clk sh7372_fsibck_clk; extern struct clk sh7372_fsidiva_clk; extern struct clk sh7372_fsidivb_clk; #endif /* __ASM_SH7372_H__ */ Loading
arch/arm/mach-shmobile/Kconfig +2 −0 Original line number Diff line number Diff line Loading @@ -116,4 +116,6 @@ endmenu config SH_CLK_CPG bool source "drivers/sh/Kconfig" endif
arch/arm/mach-shmobile/board-ap4evb.c +45 −1 Original line number Diff line number Diff line Loading @@ -565,12 +565,50 @@ static struct platform_device *qhd_devices[] __initdata = { /* FSI */ #define IRQ_FSI evt2irq(0x1840) static int fsi_set_rate(int is_porta, int rate) { struct clk *fsib_clk; struct clk *fdiv_clk = &sh7372_fsidivb_clk; int ret; /* set_rate is not needed if port A */ if (is_porta) return 0; fsib_clk = clk_get(NULL, "fsib_clk"); if (IS_ERR(fsib_clk)) return -EINVAL; switch (rate) { case 48000: clk_set_rate(fsib_clk, clk_round_rate(fsib_clk, 85428000)); clk_set_rate(fdiv_clk, clk_round_rate(fdiv_clk, 12204000)); ret = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64; break; default: pr_err("unsupported rate in FSI2 port B\n"); ret = -EINVAL; break; } clk_put(fsib_clk); return ret; } static struct sh_fsi_platform_info fsi_info = { .porta_flags = SH_FSI_BRS_INV | SH_FSI_OUT_SLAVE_MODE | SH_FSI_IN_SLAVE_MODE | SH_FSI_OFMT(PCM) | SH_FSI_IFMT(PCM), .portb_flags = SH_FSI_BRS_INV | SH_FSI_BRM_INV | SH_FSI_LRS_INV | SH_FSI_OFMT(SPDIF), .set_rate = fsi_set_rate, }; static struct resource fsi_resources[] = { Loading Loading @@ -634,6 +672,7 @@ static struct platform_device lcdc1_device = { static struct sh_mobile_hdmi_info hdmi_info = { .lcd_chan = &sh_mobile_lcdc1_info.ch[0], .lcd_dev = &lcdc1_device.dev, .flags = HDMI_SND_SRC_SPDIF, }; static struct resource hdmi_resources[] = { Loading Loading @@ -992,6 +1031,7 @@ static void __init ap4evb_map_io(void) #define GPIO_PORT9CR 0xE6051009 #define GPIO_PORT10CR 0xE605100A #define USCCR1 0xE6058144 static void __init ap4evb_init(void) { u32 srcr4; Loading Loading @@ -1062,7 +1102,7 @@ static void __init ap4evb_init(void) /* setup USB phy */ __raw_writew(0x8a0a, 0xE6058130); /* USBCR2 */ /* enable FSI2 */ /* enable FSI2 port A (ak4643) */ gpio_request(GPIO_FN_FSIAIBT, NULL); gpio_request(GPIO_FN_FSIAILR, NULL); gpio_request(GPIO_FN_FSIAISLD, NULL); Loading @@ -1079,6 +1119,10 @@ static void __init ap4evb_init(void) gpio_request(GPIO_PORT41, NULL); gpio_direction_input(GPIO_PORT41); /* setup FSI2 port B (HDMI) */ gpio_request(GPIO_FN_FSIBCK, NULL); __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ /* set SPU2 clock to 119.6 MHz */ clk = clk_get(NULL, "spu_clk"); if (!IS_ERR(clk)) { Loading
arch/arm/mach-shmobile/clock-sh7372.c +102 −0 Original line number Diff line number Diff line Loading @@ -50,6 +50,9 @@ #define SMSTPCR3 0xe615013c #define SMSTPCR4 0xe6150140 #define FSIDIVA 0xFE1F8000 #define FSIDIVB 0xFE1F8008 /* Platforms must set frequency on their DV_CLKI pin */ struct clk sh7372_dv_clki_clk = { }; Loading Loading @@ -288,6 +291,7 @@ struct clk sh7372_pllc2_clk = { .ops = &pllc2_clk_ops, .parent = &extal1_div2_clk, .freq_table = pllc2_freq_table, .nr_freqs = ARRAY_SIZE(pllc2_freq_table) - 1, .parent_table = pllc2_parent, .parent_num = ARRAY_SIZE(pllc2_parent), }; Loading Loading @@ -417,6 +421,101 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2), }; /* FSI DIV */ static unsigned long fsidiv_recalc(struct clk *clk) { unsigned long value; value = __raw_readl(clk->mapping->base); if ((value & 0x3) != 0x3) return 0; value >>= 16; if (value < 2) return 0; return clk->parent->rate / value; } static long fsidiv_round_rate(struct clk *clk, unsigned long rate) { return clk_rate_div_range_round(clk, 2, 0xffff, rate); } static void fsidiv_disable(struct clk *clk) { __raw_writel(0, clk->mapping->base); } static int fsidiv_enable(struct clk *clk) { unsigned long value; value = __raw_readl(clk->mapping->base) >> 16; if (value < 2) { fsidiv_disable(clk); return -ENOENT; } __raw_writel((value << 16) | 0x3, clk->mapping->base); return 0; } static int fsidiv_set_rate(struct clk *clk, unsigned long rate, int algo_id) { int idx; if (clk->parent->rate == rate) { fsidiv_disable(clk); return 0; } idx = (clk->parent->rate / rate) & 0xffff; if (idx < 2) return -ENOENT; __raw_writel(idx << 16, clk->mapping->base); return fsidiv_enable(clk); } static struct clk_ops fsidiv_clk_ops = { .recalc = fsidiv_recalc, .round_rate = fsidiv_round_rate, .set_rate = fsidiv_set_rate, .enable = fsidiv_enable, .disable = fsidiv_disable, }; static struct clk_mapping sh7372_fsidiva_clk_mapping = { .phys = FSIDIVA, .len = 8, }; struct clk sh7372_fsidiva_clk = { .ops = &fsidiv_clk_ops, .parent = &div6_reparent_clks[DIV6_FSIA], /* late install */ .mapping = &sh7372_fsidiva_clk_mapping, }; static struct clk_mapping sh7372_fsidivb_clk_mapping = { .phys = FSIDIVB, .len = 8, }; struct clk sh7372_fsidivb_clk = { .ops = &fsidiv_clk_ops, .parent = &div6_reparent_clks[DIV6_FSIB], /* late install */ .mapping = &sh7372_fsidivb_clk_mapping, }; static struct clk *late_main_clks[] = { &sh7372_fsidiva_clk, &sh7372_fsidivb_clk, }; enum { MSTP001, MSTP131, MSTP130, MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, Loading Loading @@ -585,6 +684,9 @@ void __init sh7372_clock_init(void) if (!ret) ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) ret = clk_register(late_main_clks[k]); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); if (!ret) Loading
arch/arm/mach-shmobile/include/mach/gpio.h +2 −2 Original line number Diff line number Diff line Loading @@ -35,12 +35,12 @@ static inline int gpio_cansleep(unsigned gpio) static inline int gpio_to_irq(unsigned gpio) { return -ENOSYS; return __gpio_to_irq(gpio); } static inline int irq_to_gpio(unsigned int irq) { return -EINVAL; return -ENOSYS; } #endif /* CONFIG_GPIOLIB */ Loading
arch/arm/mach-shmobile/include/mach/sh7372.h +2 −0 Original line number Diff line number Diff line Loading @@ -464,5 +464,7 @@ extern struct clk sh7372_dv_clki_div2_clk; extern struct clk sh7372_pllc2_clk; extern struct clk sh7372_fsiack_clk; extern struct clk sh7372_fsibck_clk; extern struct clk sh7372_fsidiva_clk; extern struct clk sh7372_fsidivb_clk; #endif /* __ASM_SH7372_H__ */