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Commit 6524e494 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: align with VBIOS to support new AVFS structure 



Align the driver with the latest vbios structures.

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 73ba2d5c

drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

+7 −14
Original line number Diff line number Diff line
@@ -314,52 +314,45 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr, 
			le32_to_cpu(profile->gb_vdroop_table_ckson_a2);

	param->ulGbFuseTableCksoffM1 =

			le32_to_cpu(profile->avfsgb_fuse_table_cksoff_m1);

	param->usGbFuseTableCksoffM2 =

	param->ulGbFuseTableCksoffM2 =

			le16_to_cpu(profile->avfsgb_fuse_table_cksoff_m2);

	param->ulGbFuseTableCksoffB =

			le32_to_cpu(profile->avfsgb_fuse_table_cksoff_b);

	param->ulGbFuseTableCksonM1 =

			le32_to_cpu(profile->avfsgb_fuse_table_ckson_m1);

	param->usGbFuseTableCksonM2 =

	param->ulGbFuseTableCksonM2 =

			le16_to_cpu(profile->avfsgb_fuse_table_ckson_m2);

	param->ulGbFuseTableCksonB =

			le32_to_cpu(profile->avfsgb_fuse_table_ckson_b);

	param->usMaxVoltage025mv =

			le16_to_cpu(profile->max_voltage_0_25mv);

	param->ucEnableGbVdroopTableCksoff =

			profile->enable_gb_vdroop_table_cksoff;



	param->ucEnableGbVdroopTableCkson =

			profile->enable_gb_vdroop_table_ckson;

	param->ucEnableGbFuseTableCksoff =

			profile->enable_gb_fuse_table_cksoff;

	param->ucEnableGbFuseTableCkson =

			profile->enable_gb_fuse_table_ckson;

	param->usPsmAgeComfactor =

			le16_to_cpu(profile->psm_age_comfactor);

	param->ucEnableApplyAvfsCksoffVoltage =

			profile->enable_apply_avfs_cksoff_voltage;



	param->ulDispclk2GfxclkM1 =

			le32_to_cpu(profile->dispclk2gfxclk_a);

	param->usDispclk2GfxclkM2 =

	param->ulDispclk2GfxclkM2 =

			le16_to_cpu(profile->dispclk2gfxclk_b);

	param->ulDispclk2GfxclkB =

			le32_to_cpu(profile->dispclk2gfxclk_c);

	param->ulDcefclk2GfxclkM1 =

			le32_to_cpu(profile->dcefclk2gfxclk_a);

	param->usDcefclk2GfxclkM2 =

	param->ulDcefclk2GfxclkM2 =

			le16_to_cpu(profile->dcefclk2gfxclk_b);

	param->ulDcefclk2GfxclkB =

			le32_to_cpu(profile->dcefclk2gfxclk_c);

	param->ulPixelclk2GfxclkM1 =

			le32_to_cpu(profile->pixclk2gfxclk_a);

	param->usPixelclk2GfxclkM2 =

	param->ulPixelclk2GfxclkM2 =

			le16_to_cpu(profile->pixclk2gfxclk_b);

	param->ulPixelclk2GfxclkB =

			le32_to_cpu(profile->pixclk2gfxclk_c);

	param->ulPhyclk2GfxclkM1 =

			le32_to_cpu(profile->phyclk2gfxclk_a);

	param->usPhyclk2GfxclkM2 =

	param->ulPhyclk2GfxclkM2 =

			le16_to_cpu(profile->phyclk2gfxclk_b);

	param->ulPhyclk2GfxclkB =

			le32_to_cpu(profile->phyclk2gfxclk_c);

drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h

+12 −12
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ struct pp_atomfwctrl_clock_dividers_soc15 { 
struct pp_atomfwctrl_avfs_parameters {

	uint32_t   ulMaxVddc;

	uint32_t   ulMinVddc;

	uint8_t    ucMaxVidStep;



	uint32_t   ulMeanNsigmaAcontant0;

	uint32_t   ulMeanNsigmaAcontant1;

	uint32_t   ulMeanNsigmaAcontant2;
@@ -82,30 +82,30 @@ struct pp_atomfwctrl_avfs_parameters { 
	uint32_t   ulGbVdroopTableCksonA0;

	uint32_t   ulGbVdroopTableCksonA1;

	uint32_t   ulGbVdroopTableCksonA2;



	uint32_t   ulGbFuseTableCksoffM1;

	uint16_t   usGbFuseTableCksoffM2;

	uint32_t   ulGbFuseTableCksoffB;\

	uint32_t   ulGbFuseTableCksoffM2;

	uint32_t   ulGbFuseTableCksoffB;



	uint32_t   ulGbFuseTableCksonM1;

	uint16_t   usGbFuseTableCksonM2;

	uint32_t   ulGbFuseTableCksonM2;

	uint32_t   ulGbFuseTableCksonB;

	uint16_t   usMaxVoltage025mv;

	uint8_t    ucEnableGbVdroopTableCksoff;



	uint8_t    ucEnableGbVdroopTableCkson;

	uint8_t    ucEnableGbFuseTableCksoff;

	uint8_t    ucEnableGbFuseTableCkson;

	uint16_t   usPsmAgeComfactor;

	uint8_t    ucEnableApplyAvfsCksoffVoltage;



	uint32_t   ulDispclk2GfxclkM1;

	uint16_t   usDispclk2GfxclkM2;

	uint32_t   ulDispclk2GfxclkM2;

	uint32_t   ulDispclk2GfxclkB;

	uint32_t   ulDcefclk2GfxclkM1;

	uint16_t   usDcefclk2GfxclkM2;

	uint32_t   ulDcefclk2GfxclkM2;

	uint32_t   ulDcefclk2GfxclkB;

	uint32_t   ulPixelclk2GfxclkM1;

	uint16_t   usPixelclk2GfxclkM2;

	uint32_t   ulPixelclk2GfxclkM2;

	uint32_t   ulPixelclk2GfxclkB;

	uint32_t   ulPhyclk2GfxclkM1;

	uint16_t   usPhyclk2GfxclkM2;

	uint32_t   ulPhyclk2GfxclkM2;

	uint32_t   ulPhyclk2GfxclkB;

};

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

+49 −42
Original line number Diff line number Diff line
@@ -2073,66 +2073,70 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) 
		result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);

		if (!result) {

			pp_table->MinVoltageVid = (uint8_t)

					convert_to_vid((uint16_t)(avfs_params.ulMaxVddc));

			pp_table->MaxVoltageVid = (uint8_t)

					convert_to_vid((uint16_t)(avfs_params.ulMinVddc));

			pp_table->BtcGbVdroopTableCksOn.a0 =

					cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0);

			pp_table->BtcGbVdroopTableCksOn.a1 =

					cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1);

			pp_table->BtcGbVdroopTableCksOn.a2 =

					cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2);

			pp_table->MaxVoltageVid = (uint8_t)

					convert_to_vid((uint16_t)(avfs_params.ulMaxVddc));



			pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0);

			pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1);

			pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2);

			pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);

			pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean);

			pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);

			pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor);



			pp_table->BtcGbVdroopTableCksOff.a0 =

					cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0);

			pp_table->BtcGbVdroopTableCksOff.a0_shift = 20;

			pp_table->BtcGbVdroopTableCksOff.a1 =

					cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1);

			pp_table->BtcGbVdroopTableCksOff.a1_shift = 20;

			pp_table->BtcGbVdroopTableCksOff.a2 =

					cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2);

			pp_table->BtcGbVdroopTableCksOff.a2_shift = 20;



			pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson;

			pp_table->BtcGbVdroopTableCksOn.a0 =

					cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0);

			pp_table->BtcGbVdroopTableCksOn.a0_shift = 20;

			pp_table->BtcGbVdroopTableCksOn.a1 =

					cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1);

			pp_table->BtcGbVdroopTableCksOn.a1_shift = 20;

			pp_table->BtcGbVdroopTableCksOn.a2 =

					cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2);

			pp_table->BtcGbVdroopTableCksOn.a2_shift = 20;



			pp_table->AvfsGbCksOn.m1 =

					cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);

			pp_table->AvfsGbCksOn.m2 =

					cpu_to_le16(avfs_params.usGbFuseTableCksonM2);

					cpu_to_le16(avfs_params.ulGbFuseTableCksonM2);

			pp_table->AvfsGbCksOn.b =

					cpu_to_le32(avfs_params.ulGbFuseTableCksonB);

			pp_table->AvfsGbCksOn.m1_shift = 24;

			pp_table->AvfsGbCksOn.m2_shift = 12;

			pp_table->AvfsGbCksOn.b_shift = 0;



			pp_table->OverrideAvfsGbCksOn =

					avfs_params.ucEnableGbFuseTableCkson;

			pp_table->AvfsGbCksOff.m1 =

					cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);

			pp_table->AvfsGbCksOff.m2 =

					cpu_to_le16(avfs_params.usGbFuseTableCksoffM2);

					cpu_to_le16(avfs_params.ulGbFuseTableCksoffM2);

			pp_table->AvfsGbCksOff.b =

					cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);

			pp_table->AvfsGbCksOff.m1_shift = 24;

			pp_table->AvfsGbCksOff.m2_shift = 12;

			pp_table->AvfsGbCksOff.b_shift = 0;



			pp_table->AConstant[0] =

					cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0);

			pp_table->AConstant[1] =

					cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1);

			pp_table->AConstant[2] =

					cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2);

			pp_table->DC_tol_sigma =

					cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);

			pp_table->Platform_mean =

					cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean);

			pp_table->PSM_Age_CompFactor =

					cpu_to_le16(avfs_params.usPsmAgeComfactor);

			pp_table->Platform_sigma =

					cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);



			for (i = 0; i < dep_table->count; i++)

				pp_table->StaticVoltageOffsetVid[i] = (uint8_t)

						(dep_table->entries[i].sclk_offset *

			for (i = 0; i < dep_table->count; i++) {

				if (dep_table->entries[i].sclk_offset == 0)

					pp_table->StaticVoltageOffsetVid[i] = 248;

				else

					pp_table->StaticVoltageOffsetVid[i] =

						(uint8_t)(dep_table->entries[i].sclk_offset *

								VOLTAGE_VID_OFFSET_SCALE2 /

								VOLTAGE_VID_OFFSET_SCALE1);



			pp_table->OverrideBtcGbCksOn =

					avfs_params.ucEnableGbVdroopTableCkson;

			pp_table->OverrideAvfsGbCksOn =

					avfs_params.ucEnableGbFuseTableCkson;

			}



			if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=

					data->disp_clk_quad_eqn_a) &&
@@ -2141,20 +2145,21 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) 
				pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =

						(int32_t)data->disp_clk_quad_eqn_a;

				pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =

						(int16_t)data->disp_clk_quad_eqn_b;

						(int32_t)data->disp_clk_quad_eqn_b;

				pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =

						(int32_t)data->disp_clk_quad_eqn_c;

			} else {

				pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =

						(int32_t)avfs_params.ulDispclk2GfxclkM1;

				pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =

						(int16_t)avfs_params.usDispclk2GfxclkM2;

						(int32_t)avfs_params.ulDispclk2GfxclkM2;

				pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =

						(int32_t)avfs_params.ulDispclk2GfxclkB;

			}



			pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24;

			pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12;

			pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 0;



			if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=

					data->dcef_clk_quad_eqn_a) &&
@@ -2163,20 +2168,21 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) 
				pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =

						(int32_t)data->dcef_clk_quad_eqn_a;

				pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =

						(int16_t)data->dcef_clk_quad_eqn_b;

						(int32_t)data->dcef_clk_quad_eqn_b;

				pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =

						(int32_t)data->dcef_clk_quad_eqn_c;

			} else {

				pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =

						(int32_t)avfs_params.ulDcefclk2GfxclkM1;

				pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =

						(int16_t)avfs_params.usDcefclk2GfxclkM2;

						(int32_t)avfs_params.ulDcefclk2GfxclkM2;

				pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =

						(int32_t)avfs_params.ulDcefclk2GfxclkB;

			}



			pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24;

			pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12;

			pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 0;



			if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=

					data->pixel_clk_quad_eqn_a) &&
@@ -2185,14 +2191,14 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) 
				pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =

						(int32_t)data->pixel_clk_quad_eqn_a;

				pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =

						(int16_t)data->pixel_clk_quad_eqn_b;

						(int32_t)data->pixel_clk_quad_eqn_b;

				pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =

						(int32_t)data->pixel_clk_quad_eqn_c;

			} else {

				pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =

						(int32_t)avfs_params.ulPixelclk2GfxclkM1;

				pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =

						(int16_t)avfs_params.usPixelclk2GfxclkM2;

						(int32_t)avfs_params.ulPixelclk2GfxclkM2;

				pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =

						(int32_t)avfs_params.ulPixelclk2GfxclkB;

			}
@@ -2207,20 +2213,21 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) 
				pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =

						(int32_t)data->phy_clk_quad_eqn_a;

				pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =

						(int16_t)data->phy_clk_quad_eqn_b;

						(int32_t)data->phy_clk_quad_eqn_b;

				pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =

						(int32_t)data->phy_clk_quad_eqn_c;

			} else {

				pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =

						(int32_t)avfs_params.ulPhyclk2GfxclkM1;

				pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =

						(int16_t)avfs_params.usPhyclk2GfxclkM2;

						(int32_t)avfs_params.ulPhyclk2GfxclkM2;

				pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =

						(int32_t)avfs_params.ulPhyclk2GfxclkB;

			}



			pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24;

			pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12;

			pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 0;

		} else {

			data->smu_features[GNLD_AVFS].supported = false;

		}