Merge 8e3910618f1575eb0d69014b6b14649147ed603c on remote branch (6514ddc0) · Commits · e / devices / android_kernel_fairphone_FP4

bindings/arm/msm/msm.txt

+4 −0

Original line number	Diff line number	Diff line
		@@ -56,6 +56,9 @@ SoCs:
		- BENGAL
		compatible = "qcom,bengal"

		- SCUBA
		compatible = "qcom,scuba"

		- SDMSHRIKE
		compatible = "qcom,sdmshrike"

		@@ -181,6 +184,7 @@ compatible = "qcom,lagoon-rumi"
		compatible = "qcom,bengal-rumi"
		compatible = "qcom,bengal-qrd"
		compatible = "qcom,bengal-idp"
		compatible = "qcom,scuba-rumi"
		compatible = "qcom,sdmshrike-rumi"
		compatible = "qcom,sdmshrike-mtp"
		compatible = "qcom,sdmshrike-cdp"

bindings/arm/msm/spss_utils.txt

+30 −12

Original line number	Diff line number	Diff line
		@@ -9,29 +9,47 @@ The communication with SPSS is done via spcom driver, using glink.
		The spss_utils driver selects the SPSS firmware file,
		according to a dedicated fuse and the platform HW version.

		The spss_utils driver supports SPU Insider Attack Resistance (IAR) Feature.
		SPU ROM code (PBL) expects a unique cmac for the spu firmware and spu apps.
		The spss_utils driver registers an IAR callback to the PIL notification driver.
		When SPU reset detected (SSR) the PIL calls the IAR callback to place the
		required cmac in shared memory in DDR.

		Required properties:
		-compatible : should be "qcom,spss_utils"
		-qcom,spss-fuse1-addr: fuse1 register physical address
		-qcom,spss-fuse1-bit: fuse1 relevant bit
		-qcom,spss-fuse2-addr: fuse2 register physical address
		-qcom,spss-fuse2-bit: fuse2 relevant bit
		-qcom,spss-fuse3-addr: fuse3 register physical address
		-qcom,spss-fuse3-bit: fuse3 relevant bit
		-qcom,spss-fuse4-addr: fuse4 register physical address
		-qcom,spss-fuse4-bit: fuse4 relevant bit
		-qcom,spss-dev-firmware-name: dev firmware file name
		-qcom,spss-test-firmware-name: test firmware file name
		-qcom,spss-prod-firmware-name: production firmware file name
		-qcom,spss-debug-reg-addr: debug register physical address
		-qcom,spss-emul-type-reg-addr: soc emulation type register physical address
		-qcom,pil-mem: pointer to pil_spss_mem node, to get PIL memory address
		-qcom,pil-mem: PIL memory size, spu firmware size is padded to 960 KB

		Example:
		qcom,spss_utils {
		spss_utils: qcom,spss_utils {
		compatible = "qcom,spss-utils";

		qcom,spss-fuse1-addr = <0x007841c4>;
		qcom,spss-fuse1-addr = <0x00780234>;
		qcom,spss-fuse1-bit = <27>;
		qcom,spss-fuse2-addr = <0x007841c4>;
		qcom,spss-fuse2-addr = <0x00780234>;
		qcom,spss-fuse2-bit = <26>;
		qcom,spss-fuse3-addr = <0x007801E8>;
		qcom,spss-fuse3-bit = <10>;
		qcom,spss-fuse4-addr = <0x00780218>;
		qcom,spss-fuse4-bit = <1>;
		qcom,spss-dev-firmware-name = "spss1d"; /* 8 chars max */
		qcom,spss-test-firmware-name = "spss1t"; /* 8 chars max */
		qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */
		qcom,spss-debug-reg-addr = <0x01886020>;
		qcom,spss-emul-type-reg-addr = <0x01fc8004>;
		pil-mem = <&pil_spss_mem>;
		qcom,pil-size = <0x0F0000>;
		};

bindings/bus/mhi.txt

+13 −0

Original line number	Diff line number	Diff line
		@@ -33,6 +33,19 @@ Main node properties:
		Set the length of buffer size to allocate. If not default
		size MHI_MAX_MTU will be used.

		- mhi,name
		Usage: optional
		Value type: <string>
		Definition: Name assigned to the controller for cases where caller is not an
		MHI client.
		Use "esoc0" for qcom modems such as SDX*.

		- mhi,sfr-support
		Usage: optional
		Value type: <bool>
		Definition: Set to true if MHI device supports sending subsystem failure
		reason upon assert in case PCIe link is functional.

		============================
		mhi channel node properties:
		============================

bindings/clock/qcom,npucc.txt

+8 −1

Original line number	Diff line number	Diff line
		@@ -5,6 +5,7 @@ Required properties :
		- compatible: Should be "qcom,npucc-kona",
		"qcom,npucc-kona-v2",
		"qcom,lito-npucc",
		"qcom,lito-npucc-v2",
		"qcom,lagoon-npucc".
		- reg: Shall contain base register addresses and sizes.
		- reg-names: Names of the register bases listed in the same order as
		@@ -15,6 +16,10 @@ Required properties :
		- #clock-cells: Shall contain 1.
		- #reset-cells: Shall contain 1.

		Optional properties:
		- nvmem-cells: list of phandle to the nvmem data cells.
		- nvmem-cell-names: names for the each nvmem-cells specified.

		Example:

		clock_npucc: qcom,npucc@9980000 {
		@@ -24,6 +29,8 @@ clock_npucc: qcom,npucc@9980000 {
		<0x9810000 0x10000>;
		reg-names = "cc", "qdsp6ss", "qdsp6ss_pll";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		nvmem-cells = <&npu_efuse>;
		nvmem-cell-names = "npu-bin";
		#clock-cells = <1>;
		#reset-cells = <1>;
		};

bindings/extcon/extcon-storage-cd-gpio.txt

deleted100644 → 0

+0 −30

Original line number	Diff line number	Diff line
		Storage card detect GPIO based Extcon device

		This is a virtual device used to generate GPIO states from the GPIO ID pin
		connected to a GPIO pin.

		Required properties:
		- compatible: Should be "extcon-storage-cd-gpio"
		- extcon-id: The unique id of specific external connector.
		Valid range is 0 (EXTCON_NONE) to 63 (EXTCON_NUM).
		Refer include/linux/extcon.h for details.
		- gpio: Specify GPIO (see gpio binding)
		- irq-flags: interrupt flags (edge/level). Refer to "include/dt-bindings/interrupt-controller/irq.h"
		- pinctrl-names, pinctrl-0, pinctrl-1,.. pinctrl-n: Refer to "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt"
		for these optional properties

		Example:
		extcon_storage_cd {
		compatible = "extcon-storage-cd-gpio";
		extcon-id = <62>; /* EXTCON_MECHANICAL */
		gpio = <&tlmm 126 GPIO_ACTIVE_LOW>;
		irq-flags = <IRQ_TYPE_EDGE_BOTH>;
		}

		&ufshc_card {
		extcon = <&extcon_storage_cd>;
		};

		&sd_card {
		extcon = <&extcon_storage_cd>;
		};