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Commit 64ded09d authored by Thor Thayer's avatar Thor Thayer Committed by Dinh Nguyen
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ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entry 



Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.

Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
parent 95c16caa

arch/arm/boot/dts/socfpga_arria10.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -603,6 +603,21 @@ 
			reg = <0xffe00000 0x40000>;

		};



		eccmgr: eccmgr@ffd06000 {

			compatible = "altr,socfpga-a10-ecc-manager";

			altr,sysmgr-syscon = <&sysmgr>;

			#address-cells = <1>;

			#size-cells = <1>;

			interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,

				     <0 0 IRQ_TYPE_LEVEL_HIGH>;

			ranges;



			l2-ecc@ffd06010 {

				compatible = "altr,socfpga-a10-l2-ecc";

				reg = <0xffd06010 0x4>;

			};

		};



		rst: rstmgr@ffd05000 {

			#reset-cells = <1>;

			compatible = "altr,rst-mgr";