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Commit 64d6ea60 authored by Shawn Lin's avatar Shawn Lin Committed by Bjorn Helgaas
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PCI: rockchip: Set PCI_EXP_LNKSTA_SLC in the Root Port 



All platforms using Rockchip use a common clock for the Root Port and the
slot connected to it. Indicate this by setting the Slot Clock Configuration
(PCI_EXP_LNKSTA_SLC) bit in the Root Port's Link Status.

Per the Implementation Note in the spec (PCIe r3.1, sec 7.8.7), if the
downstream component also sets PCI_EXP_LNKSTA_SLC, software may set the
Common Clock Configuration (PCI_EXP_LNKCTL_CCC) bits on both ends of the
Link. This is done by pcie_aspm_configure_common_clock().

Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Cc: Brian Norris <briannorris@chromium.org>
Cc: jeffy.chen <jeffy.chen@rock-chips.com>
parent 55021718

drivers/pci/host/pcie-rockchip.c

+1 −1
Original line number Diff line number Diff line
@@ -598,7 +598,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) 


	/* Set RC's clock architecture as common clock */

	status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);

	status |= PCI_EXP_LNKCTL_CCC;

	status |= PCI_EXP_LNKSTA_SLC << 16;

	rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);



	/* Set RC's RCB to 128 */