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Commit 64c0606a authored by Jilai Wang's avatar Jilai Wang
Browse files

ARM: dts: msm: Update NPU FMAX for kona v2 and lito 

This change is to update NPU FMAX for kona v2 and lito.

Change-Id: I166ccadc52b933651a36aaab003cf11faf6cd132
parent 0db572ee

qcom/kona-v2.dtsi

+213 −0
Original line number Diff line number Diff line
@@ -173,3 +173,216 @@ 
&cpu4_qoslatmon {

	qcom,cachemiss-ev = <0x1000>;

};



/* NPU overrides */

&msm_npu {

	qcom,npu-pwrlevels {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "qcom,npu-pwrlevels";

		initial-pwrlevel = <5>;

		qcom,npu-pwrlevel@0 {

			reg = <0>;

			vreg = <1>;

			clk-freq = <19200000

				100000000

				300000000

				300000000

				300000000

				300000000

				200000000

				40000000

				300000000

				100000000

				19200000

				50000000

				50000000

				100000000

				100000000

				100000000

				19200000

				100000000

				19200000

				50000000

				200000000

				200000000

				60000000

				50000000

				19200000

				300000000

				300000000

				19200000

				300000000>;

		};



		qcom,npu-pwrlevel@1 {

			reg = <1>;

			vreg = <2>;

			clk-freq = <19200000

				200000000

				406000000

				406000000

				406000000

				406000000

				267000000

				40000000

				403000000

				200000000

				19200000

				50000000

				50000000

				200000000

				200000000

				200000000

				19200000

				200000000

				19200000

				50000000

				406000000

				406000000

				120000000

				50000000

				19200000

				406000000

				406000000

				19200000

				400000000>;

		};



		qcom,npu-pwrlevel@2 {

			reg = <2>;

			vreg = <3>;

			clk-freq = <19200000

				333000000

				533000000

				533000000

				533000000

				533000000

				403000000

				75000000

				533000000

				214000000

				19200000

				50000000

				100000000

				214000000

				214000000

				214000000

				19200000

				214000000

				19200000

				50000000

				533000000

				533000000

				240000000

				50000000

				19200000

				533000000

				533000000

				19200000

				500000000>;

		};



		qcom,npu-pwrlevel@3 {

			reg = <3>;

			vreg = <4>;

			clk-freq = <19200000

				428000000

				730000000

				730000000

				730000000

				730000000

				533000000

				75000000

				700000000

				300000000

				19200000

				100000000

				200000000

				300000000

				300000000

				300000000

				19200000

				300000000

				19200000

				100000000

				730000000

				730000000

				240000000

				100000000

				19200000

				730000000

				730000000

				19200000

				660000000>;

		};



		qcom,npu-pwrlevel@4 {

			reg = <4>;

			vreg = <6>;

			clk-freq = <19200000

				500000000

				920000000

				920000000

				920000000

				920000000

				700000000

				75000000

				806000000

				300000000

				19200000

				100000000

				200000000

				300000000

				300000000

				300000000

				19200000

				300000000

				19200000

				100000000

				920000000

				920000000

				30000000

				100000000

				19200000

				920000000

				920000000

				19200000

				800000000>;

		};



		qcom,npu-pwrlevel@5 {

			reg = <5>;

			vreg = <7>;

			clk-freq = <19200000

				500000000

				1000000000

				1000000000

				1000000000

				1000000000

				700000000

				75000000

				806000000

				300000000

				19200000

				100000000

				200000000

				300000000

				300000000

				300000000

				19200000

				300000000

				19200000

				100000000

				1000000000

				1000000000

				30000000

				100000000

				19200000

				1000000000

				1000000000

				19200000

				800000000>;

		};

	};

};

qcom/lito-npu.dtsi

+47 −18
Original line number Diff line number Diff line
@@ -82,21 +82,21 @@ 
				IPCC_MPROC_SIGNAL_PING>;

		mbox-names = "ipcc-glink", "ipcc-smp2p", "ipcc-ping";

		#mbox-cells = <2>;

		qcom,npubw-devs = <&npu_npu_ddr_bw>, <&npudsp_npu_ddr_bw>;

		qcom,npubw-devs = <&npu_npu_ddr_bw &npudsp_npu_ddr_bw>;

		qcom,npubw-dev-names = "ddr_bw", "dsp_ddr_bw";

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		qcom,npu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,npu-pwrlevels";

			initial-pwrlevel = <4>;

			initial-pwrlevel = <5>;

			qcom,npu-pwrlevel@0 {

				reg = <0>;

				vreg = <1>;

				clk-freq = <19200000

					100000000

					300000000

					300000000

					230000000

					230000000

					150000000

					40000000

					300000000
@@ -111,10 +111,10 @@ 
					100000000

					19200000

					50000000

					300000000

					230000000

					50000000

					19200000

					300000000

					230000000

					19200000

					300000000>;

			};
@@ -124,8 +124,8 @@ 
				vreg = <2>;

				clk-freq = <19200000

					200000000

					518400000

					518400000

					422000000

					422000000

					207000000

					40000000

					403000000
@@ -140,10 +140,10 @@ 
					200000000

					19200000

					50000000

					518400000

					422000000

					50000000

					19200000

					518400000

					422000000

					19200000

					400000000>;

			};
@@ -153,8 +153,8 @@ 
				vreg = <3>;

				clk-freq = <19200000

					333000000

					633600000

					633600000

					557000000

					557000000

					300000000

					75000000

					533000000
@@ -169,10 +169,10 @@ 
					214000000

					19200000

					50000000

					633600000

					557000000

					50000000

					19200000

					633600000

					557000000

					19200000

					500000000>;

			};
@@ -182,8 +182,8 @@ 
				vreg = <4>;

				clk-freq = <19200000

					428000000

					825600000

					825600000

					729000000

					729000000

					403000000

					75000000

					700000000
@@ -198,10 +198,10 @@ 
					300000000

					19200000

					100000000

					825600000

					729000000

					100000000

					19200000

					825600000

					729000000

					19200000

					660000000>;

			};
@@ -209,6 +209,35 @@ 
			qcom,npu-pwrlevel@4 {

				reg = <4>;

				vreg = <6>;

				clk-freq = <19200000

					500000000

					844000000

					844000000

					533000000

					75000000

					806000000

					300000000

					19200000

					100000000

					200000000

					300000000

					300000000

					300000000

					19200000

					300000000

					19200000

					100000000

					844000000

					100000000

					19200000

					844000000

					19200000

					800000000>;

			};



			qcom,npu-pwrlevel@5 {

				reg = <5>;

				vreg = <7>;

				clk-freq = <19200000

					500000000

					1000000000