Commit 64183ba3 authored Jun 07, 2019 by Taniya Committed by Gerrit - the friendly Code Review server Jun 10, 2019

ARM: dts: msm: Add cycle counters property for LITO

LITO cpufreq hw requires to read the cycle counters of core-0 of the
frequency domain.

Change-Id: I0461372ad65744feaf12d0a327771c890e82b349

parent 419ea2b7

qcom/lito.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -1400,6 +1400,7 @@
		"freq-domain2";
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
		clock-names = "xo", "alternate";
		qcom,no-accumulative-counter;
		#freq-domain-cells = <2>;
		};