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Commit 63e138ab authored May 18, 2018 by Rex Zhu Committed by Alex Deucher May 24, 2018

drm/amd/pp: Fix static checker warning



error: uninitialized symbol 'xxxx'

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent e1d1a772

drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c

+10 −14

Original line number	Original line	Diff line number	Diff line
	@@ -1104,10 +1104,8 @@ int atomctrl_get_voltage_evv_on_sclk(
	GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),		GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
	(uint32_t *)&get_voltage_info_param_space);		(uint32_t *)&get_voltage_info_param_space);

	if (0 != result)		*voltage = result ? 0 :
	return result;		le16_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)

	voltage = le16_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 )
	(&get_voltage_info_param_space))->usVoltageLevel);		(&get_voltage_info_param_space))->usVoltageLevel);

	return result;		return result;
	@@ -1312,8 +1310,7 @@ int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
	result = amdgpu_atom_execute_table(adev->mode_info.atom_context,		result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),		GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
	(uint32_t *)&efuse_param);		(uint32_t *)&efuse_param);
	if (!result)		*efuse = result ? 0 : le32_to_cpu(efuse_param.ulEfuseValue) & mask;
	*efuse = le32_to_cpu(efuse_param.ulEfuseValue) & mask;

	return result;		return result;
	}		}
	@@ -1354,11 +1351,8 @@ int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_
	GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),		GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
	(uint32_t *)&get_voltage_info_param_space);		(uint32_t *)&get_voltage_info_param_space);

	if (0 != result)		*voltage = result ? 0 :
	return result;		le32_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)(&get_voltage_info_param_space))->ulVoltageLevel);

	voltage = le32_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 )
	(&get_voltage_info_param_space))->ulVoltageLevel);

	return result;		return result;
	}		}
	@@ -1552,15 +1546,17 @@ void atomctrl_get_voltage_range(struct pp_hwmgr hwmgr, uint32_t max_vddc,
	case CHIP_FIJI:		case CHIP_FIJI:
	max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 )profile)->ulMaxVddc/4);		max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 )profile)->ulMaxVddc/4);
	min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 )profile)->ulMinVddc/4);		min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 )profile)->ulMinVddc/4);
	break;		return;
	case CHIP_POLARIS11:		case CHIP_POLARIS11:
	case CHIP_POLARIS10:		case CHIP_POLARIS10:
	case CHIP_POLARIS12:		case CHIP_POLARIS12:
	max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 )profile)->ulMaxVddc/100);		max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 )profile)->ulMaxVddc/100);
	min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 )profile)->ulMinVddc/100);		min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 )profile)->ulMinVddc/100);
	break;
	default:
	return;		return;
			default:
			break;
	}		}
	}		}
			*max_vddc = 0;
			*min_vddc = 0;
	}		}

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -860,7 +860,8 @@ static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr)
	struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;		struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
	struct phm_ppt_v1_information *table_info =		struct phm_ppt_v1_information *table_info =
	(struct phm_ppt_v1_information *)(hwmgr->pptable);		(struct phm_ppt_v1_information *)(hwmgr->pptable);
	uint32_t min_vddc, max_vddc;		uint32_t min_vddc = 0;
			uint32_t max_vddc = 0;

	if (!table_info)		if (!table_info)
	return;		return;

drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c

+2 −4

Original line number	Original line	Diff line number	Diff line
	@@ -283,11 +283,9 @@ int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t

	result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);		result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);

	if (result)		*value = result ? 0 : cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
	return result;

	*value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);		return result;
	return 0;
	}		}

	int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit)		int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit)