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Commit 634e651b authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add IPA device configuration for lito"

parents 8c99f8b6 2ae28979

qcom/lito-smp2p.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -23,6 +23,18 @@ 
			interrupt-controller;

			#interrupt-cells = <2>;

		};



		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {

			qcom,entry-name = "ipa";

			#qcom,smem-state-cells = <1>;

		};



		 /* ipa - inbound entry from mss */

		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {

			qcom,entry-name = "ipa";

			interrupt-controller;

			#interrupt-cells = <2>;

		};

	};



	qcom,smp2p-adsp {

qcom/lito.dtsi

+125 −0
Original line number Diff line number Diff line
@@ -2000,6 +2000,131 @@ 
		BW_OPP_ENTRY( 2092, 4); /*  7980 MB/s */

		BW_OPP_ENTRY( 2736, 4); /* 10437 MB/s */

	};



	qcom,msm_gsi {

		compatible = "qcom,msm_gsi";

	};



	qcom,rmnet-ipa {

		compatible = "qcom,rmnet-ipa3";

		qcom,rmnet-ipa-ssr;

		qcom,ipa-platform-type-msm;

		qcom,ipa-advertise-sg-support;

		qcom,ipa-napi-enable;

	};



	qcom,ipa_fws {

		compatible = "qcom,pil-tz-generic";

		qcom,pas-id = <0xf>;

		qcom,firmware-name = "ipa_fws";

		qcom,pil-force-shutdown;

		memory-region = <&pil_ipa_gsi_mem>;

	};



	ipa_hw: qcom,ipa@1e00000 {

		compatible = "qcom,ipa";

		reg = <0x1e00000 0x84000>,

			<0x1e04000 0x23000>;

		reg-names = "ipa-base", "gsi-base";

		interrupts = <0 311 0>, <0 432 0>;

		interrupt-names = "ipa-irq", "gsi-irq";

		qcom,ipa-hw-ver = <18>; /* IPA core version = IPAv4.7 */

		qcom,ipa-hw-mode = <0>;

		qcom,platform-type = <1>; /* MSM platform */

		qcom,ee = <0>;

		qcom,use-ipa-tethering-bridge;

		qcom,modem-cfg-emb-pipe-flt;

		qcom,ipa-wdi2;

		qcom,ipa-wdi2_over_gsi;

		qcom,ipa-fltrt-not-hashable;

		qcom,use-ipa-pm;

		qcom,arm-smmu;

		qcom,smmu-fast-map;

		qcom,bandwidth-vote-for-ipa;

		qcom,use-64-bit-dma-mask;

		qcom,msm-bus,name = "ipa";

		qcom,msm-bus,num-cases = <5>;

		qcom,msm-bus,num-paths = <5>;

		qcom,msm-bus,vectors-KBps =

		/* No vote */

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 0 0>,

		<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 0 0>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 0>,



		/* SVS2 */

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 150000 500000>,

		<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 150000 1804000>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 75000 300000>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 76800>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 150>,



		/* SVS */

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 625000 1200000>,

		<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 625000 3072000>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 312500 700000>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 150000>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 260>,



		/* NOMINAL */

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 1250000 2400000>,

		<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 1250000 6220800>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 625000 1500000>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 400000>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 450>,



		/* TURBO */

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 2000000 3500000>,

		<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 2000000 7219000>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 1000000 1920000>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 400000>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 550>;





		qcom,bus-vector-names =

			"MIN", "SVS2", "SVS", "NOMINAL", "TURBO";

		qcom,throughput-threshold = <310 600 1000>;

		qcom,scaling-exceptions = <>;



		/* smp2p information */

		qcom,smp2p_map_ipa_1_out {

			compatible = "qcom,smp2p-map-ipa-1-out";

			qcom,smem-states = <&smp2p_ipa_1_out 0>;

			qcom,smem-state-names = "ipa-smp2p-out";

		};



		qcom,smp2p_map_ipa_1_in {

			compatible = "qcom,smp2p-map-ipa-1-in";

			interrupts-extended = <&smp2p_ipa_1_in 0 0>;

			interrupt-names = "ipa-smp2p-in";

		};

	};



	ipa_smmu_ap: ipa_smmu_ap {

		compatible = "qcom,ipa-smmu-ap-cb";

		iommus = <&apps_smmu 0x0520 0x0>;

		qcom,iommu-dma-addr-pool = <0x20000000 0x40000000>;

		/* modem tables in IMEM */

		qcom,additional-mapping = <0x146a9000 0x146a9000 0x2000>;

		dma-coherent;

		qcom,iommu-dma = "fastmap";

	};



	ipa_smmu_wlan: ipa_smmu_wlan {

		compatible = "qcom,ipa-smmu-wlan-cb";

		iommus = <&apps_smmu 0x0521 0x0>;

		/* ipa-uc ram */

		qcom,additional-mapping = <0x1ea0000 0x1ea0000 0x80000>;

		qcom,iommu-dma = "fastmap";

	};



	ipa_smmu_uc: ipa_smmu_uc {

		compatible = "qcom,ipa-smmu-uc-cb";

		iommus = <&apps_smmu 0x0522 0x0>;

		qcom,iommu-dma-addr-pool = <0x40000000 0x20000000>;

		qcom,iommu-dma = "fastmap";

	};

};



#include "lito-pinctrl.dtsi"