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Commit 62d212bd authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard
Browse files

clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs 



The PLLs on H3 have a lock bit, which will only be set to 1 when the PLL
is really working.

Add CLK_SET_RATE_UNGATE to the PLLs, otherwise it will timeout when
trying to set PLL clock frequency without enabling it.

Fixes: 0577e485 ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 2bd6bf03

drivers/clk/sunxi-ng/ccu-sun8i-h3.c

+9 −9
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux", 
				     16, 2,	/* P */

				     BIT(31),	/* gate */

				     BIT(28),	/* lock */

				     0);

				     CLK_SET_RATE_UNGATE);



/*

 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
@@ -55,7 +55,7 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 
				   0, 5,	/* M */

				   BIT(31),	/* gate */

				   BIT(28),	/* lock */

				   0);

				   CLK_SET_RATE_UNGATE);



static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",

					"osc24M", 0x0010,
@@ -67,7 +67,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", 
					297000000,	/* frac rate 1 */

					BIT(31),	/* gate */

					BIT(28),	/* lock */

					0);

					CLK_SET_RATE_UNGATE);



static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",

					"osc24M", 0x0018,
@@ -79,7 +79,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 
					297000000,	/* frac rate 1 */

					BIT(31),	/* gate */

					BIT(28),	/* lock */

					0);

					CLK_SET_RATE_UNGATE);



static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",

				    "osc24M", 0x020,
@@ -88,7 +88,7 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr", 
				    0, 2,	/* M */

				    BIT(31),	/* gate */

				    BIT(28),	/* lock */

				    0);

				    CLK_SET_RATE_UNGATE);



static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",

					   "osc24M", 0x028,
@@ -97,7 +97,7 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0", 
					   BIT(31),	/* gate */

					   BIT(28),	/* lock */

					   2,		/* post-div */

					   0);

					   CLK_SET_RATE_UNGATE);



static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",

					"osc24M", 0x0038,
@@ -109,7 +109,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", 
					297000000,	/* frac rate 1 */

					BIT(31),	/* gate */

					BIT(28),	/* lock */

					0);

					CLK_SET_RATE_UNGATE);



static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",

					   "osc24M", 0x044,
@@ -118,7 +118,7 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1", 
					   BIT(31),	/* gate */

					   BIT(28),	/* lock */

					   2,		/* post-div */

					   0);

					   CLK_SET_RATE_UNGATE);



static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",

					"osc24M", 0x0048,
@@ -130,7 +130,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", 
					297000000,	/* frac rate 1 */

					BIT(31),	/* gate */

					BIT(28),	/* lock */

					0);

					CLK_SET_RATE_UNGATE);



static const char * const cpux_parents[] = { "osc32k", "osc24M",

					     "pll-cpux" , "pll-cpux" };