Merge remote-tracking branch 'media_tree/vsp1' into generic-zpos-v8

	    <entry><constant>MEDIA_ENT_F_AUDIO_MIXER</constant></entry>

	    <entry>Audio Mixer Function Entity.</entry>

	  </row>

	  <row>

	    <entry><constant>MEDIA_ENT_F_PROC_VIDEO_COMPOSER</constant></entry>

	    <entry>Video composer (blender). An entity capable of video

		   composing must have at least two sink pads and one source

		   pad, and composes input video frames onto output video

		   frames. Composition can be performed using alpha blending,

		   color keying, raster operations (ROP), stitching or any other

		   means.

	    </entry>

	  </row>

	  <row>

	    <entry><constant>MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER</constant></entry>

	    <entry>Video pixel formatter. An entity capable of pixel formatting

		   must have at least one sink pad and one source pad. Read

		   pixel formatters read pixels from memory and perform a subset

		   of unpacking, cropping, color keying, alpha multiplication

		   and pixel encoding conversion. Write pixel formatters perform

		   a subset of dithering, pixel encoding conversion and packing

		   and write pixels to memory.

	    </entry>

	  </row>

	  <row>

	    <entry><constant>MEDIA_ENT_F_PROC_VIDEO_PIXEL_ENC_CONV</constant></entry>

	    <entry>Video pixel encoding converter. An entity capable of pixel

		   enconding conversion must have at least one sink pad and one

		   source pad, and convert the encoding of pixels received on

		   its sink pad(s) to a different encoding output on its source

		   pad(s). Pixel encoding conversion includes but isn't limited

		   to RGB to/from HSV, RGB to/from YUV and CFA (Bayer) to RGB

		   conversions.

	    </entry>

	  </row>

	  <row>

	    <entry><constant>MEDIA_ENT_F_PROC_VIDEO_LUT</constant></entry>

	    <entry>Video look-up table. An entity capable of video lookup table

		   processing must have one sink pad and one source pad. It uses

		   the values of the pixels received on its sink pad to look up

		   entries in internal tables and output them on its source pad.

		   The lookup processing can be performed on all components

		   separately or combine them for multi-dimensional table

		   lookups.

	    </entry>

	  </row>

	  <row>

	    <entry><constant>MEDIA_ENT_F_PROC_VIDEO_SCALER</constant></entry>

	    <entry>Video scaler. An entity capable of video scaling must have

		   at least one sink pad and one source pad, and scale the

		   video frame(s) received on its sink pad(s) to a different

		   resolution output on its source pad(s). The range of

		   supported scaling ratios is entity-specific and can differ

		   between the horizontal and vertical directions (in particular

		   scaling can be supported in one direction only). Binning and

		   skipping are considered as scaling.

	    </entry>

	  </row>

	  <row>

	    <entry><constant>MEDIA_ENT_F_PROC_VIDEO_STATISTICS</constant></entry>

	    <entry>Video statistics computation (histogram, 3A, ...). An entity

		   capable of statistics computation must have one sink pad and

		   one source pad. It computes statistics over the frames

		   received on its sink pad and outputs the statistics data on

		   its source pad.

	    </entry>

	  </row>

	</tbody>

      </tgroup>

    </table>

* Mediatek Video Processor Unit

Video Processor Unit is a HW video controller. It controls HW Codec including

H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert).

Required properties:

  - compatible: "mediatek,mt8173-vpu"

  - reg: Must contain an entry for each entry in reg-names.

  - reg-names: Must include the following entries:

    "tcm": tcm base

    "cfg_reg": Main configuration registers base

  - interrupts: interrupt number to the cpu.

  - clocks : clock name from clock manager

  - clock-names: must be main. It is the main clock of VPU

Optional properties:

  - memory-region: phandle to a node describing memory (see

    Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)

    to be used for VPU extended memory; if not present, VPU may be located

    anywhere in the memory

Example:

	vpu: vpu@10020000 {

		compatible = "mediatek,mt8173-vpu";

		reg = <0 0x10020000 0 0x30000>,

		      <0 0x10050000 0 0x100>;

		reg-names = "tcm", "cfg_reg";

		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&topckgen TOP_SCP_SEL>;

		clock-names = "main";

	};

Renesas R-Car Frame Compression Processor (FCP)

-----------------------------------------------

The FCP is a companion module of video processing modules in the Renesas R-Car

Gen3 SoCs. It provides data compression and decompression, data caching, and

conversion of AXI transactions in order to reduce the memory bandwidth.

There are three types of FCP: FCP for Codec (FCPC), FCP for VSP (FCPV) and FCP

for FDP (FCPF). Their configuration and behaviour depend on the module they

are paired with. These DT bindings currently support the FCPV only.

 - compatible: Must be one or more of the following

   - "renesas,r8a7795-fcpv" for R8A7795 (R-Car H3) compatible 'FCP for VSP'

   - "renesas,fcpv" for generic compatible 'FCP for VSP'

   When compatible with the generic version, nodes must list the

   SoC-specific version corresponding to the platform first, followed by the

   family-specific and/or generic versions.

 - reg: the register base and size for the device registers

 - clocks: Reference to the functional clock

Device node example

-------------------

	fcpvd1: fcp@fea2f000 {

		compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";

		reg = <0 0xfea2f000 0 0x200>;

		clocks = <&cpg CPG_MOD 602>;

	};

  - interrupts: VSP interrupt specifier.

  - clocks: A phandle + clock-specifier pair for the VSP functional clock.

Optional properties:

  - renesas,fcp: A phandle referencing the FCP that handles memory accesses

                 for the VSP. Not needed on Gen2, mandatory on Gen3.

Example: R8A7790 (R-Car H2) VSP1-S node

  - clock-names : from common clock binding: must contain "mfc",

		  corresponding to entry in the clocks property.

  - samsung,mfc-r : Base address of the first memory bank used by MFC

		    for DMA contiguous memory allocation and its size.

  - samsung,mfc-l : Base address of the second memory bank used by MFC

		    for DMA contiguous memory allocation and its size.

Optional properties:

  - power-domains : power-domain property defined with a phandle

			   to respective power domain.

  - memory-region : from reserved memory binding: phandles to two reserved

	memory regions, first is for "left" mfc memory bus interfaces,

	second if for the "right" mfc memory bus, used when no SYSMMU

	support is available

Obsolete properties:

  - samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region

	property instead

Example:

SoC specific DT entry:

	clock-names = "mfc";

};

Reserved memory specific DT entry for given board (see reserved memory binding

for more information):

reserved-memory {

	#address-cells = <1>;

	#size-cells = <1>;

	ranges;

	mfc_left: region@51000000 {

		compatible = "shared-dma-pool";

		no-map;

		reg = <0x51000000 0x800000>;

	};

	mfc_right: region@43000000 {

		compatible = "shared-dma-pool";

		no-map;

		reg = <0x43000000 0x800000>;

	};

};

Board specific DT entry:

codec@13400000 {

	samsung,mfc-r = <0x43000000 0x800000>;

	samsung,mfc-l = <0x51000000 0x800000>;

	memory-region = <&mfc_left>, <&mfc_right>;

};