clk: qcom: gpucc: Add support for GPUCC clock driver for BENGAL (623b89dc) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/clk/qcom/Kconfig

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -416,3 +416,11 @@ config SM_GCC_BENGAL
	Support for the global clock controller on Bengal devices.		Support for the global clock controller on Bengal devices.
	Say Y if you want to use peripheral devices such as UART, SPI,		Say Y if you want to use peripheral devices such as UART, SPI,
	I2C, USB, UFS, SDCC, PCIe, Camera, Video etc.		I2C, USB, UFS, SDCC, PCIe, Camera, Video etc.

			config SM_GPUCC_BENGAL
			tristate "BENGAL Graphics Clock Controller"
			select SM_GCC_BENGAL
			help
			Support for the graphics clock controller on Qualcomm Technologies, Inc
			BENGAL devices.
			Say Y if you want to support graphics controller devices.

drivers/clk/qcom/Makefile

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -57,7 +57,8 @@ obj-$(CONFIG_SM_DEBUGCC_LITO) += debugcc-lito.o
	obj-$(CONFIG_SM_DISPCC_LITO) += dispcc-lito.o		obj-$(CONFIG_SM_DISPCC_LITO) += dispcc-lito.o
	obj-$(CONFIG_SM_GCC_BENGAL) += gcc-bengal.o		obj-$(CONFIG_SM_GCC_BENGAL) += gcc-bengal.o
	obj-$(CONFIG_SM_GCC_LITO) += gcc-lito.o		obj-$(CONFIG_SM_GCC_LITO) += gcc-lito.o
			obj-$(CONFIG_SM_GPUCC_BENGAL) += gpucc-bengal.o
			obj-$(CONFIG_SM_GPUCC_LITO) += gpucc-lito.o
	obj-$(CONFIG_SM_NPUCC_LITO) += npucc-lito.o		obj-$(CONFIG_SM_NPUCC_LITO) += npucc-lito.o
	obj-$(CONFIG_SM_VIDEOCC_LITO) += videocc-lito.o		obj-$(CONFIG_SM_VIDEOCC_LITO) += videocc-lito.o
	obj-$(CONFIG_SM_GPUCC_LITO) += gpucc-lito.o
	obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o		obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o

drivers/clk/qcom/gpucc-bengal.c

0 → 100644

+517 −0

Original line number	Original line	Diff line number	Diff line
			// SPDX-License-Identifier: GPL-2.0-only
			/*
			* Copyright (c) 2019, The Linux Foundation. All rights reserved.
			*/

			#define pr_fmt(fmt) "clk: %s: " fmt, __func__

			#include <linux/kernel.h>
			#include <linux/module.h>
			#include <linux/of_device.h>
			#include <linux/of.h>
			#include <linux/regmap.h>

			#include <dt-bindings/clock/qcom,gpucc-bengal.h>

			#include "clk-alpha-pll.h"
			#include "clk-branch.h"
			#include "clk-rcg.h"
			#include "clk-regmap.h"
			#include "common.h"
			#include "vdd-level-bengal.h"

			#define CX_GMU_CBCR_SLEEP_MASK 0xf
			#define CX_GMU_CBCR_SLEEP_SHIFT 4
			#define CX_GMU_CBCR_WAKE_MASK 0xf
			#define CX_GMU_CBCR_WAKE_SHIFT 8

			static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);

			enum {
			P_BI_TCXO,
			P_CORE_BI_PLL_TEST_SE,
			P_GPLL0_OUT_MAIN,
			P_GPLL0_OUT_MAIN_DIV,
			P_GPU_CC_PLL0_2X_DIV_CLK_SRC,
			P_GPU_CC_PLL0_OUT_AUX2,
			P_GPU_CC_PLL0_OUT_MAIN,
			P_GPU_CC_PLL1_OUT_AUX,
			P_GPU_CC_PLL1_OUT_AUX2,
			P_GPU_CC_PLL1_OUT_MAIN,
			};

			static const struct parent_map gpu_cc_parent_map_0[] = {
			{ P_BI_TCXO, 0 },
			{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
			{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
			{ P_GPLL0_OUT_MAIN, 5 },
			{ P_GPLL0_OUT_MAIN_DIV, 6 },
			{ P_CORE_BI_PLL_TEST_SE, 7 },
			};

			static const char * const gpu_cc_parent_names_0[] = {
			"bi_tcxo",
			"gpu_cc_pll0_out_main",
			"gpu_cc_pll1_out_main",
			"gpll0_out_main",
			"gpll0_out_main_div",
			"core_bi_pll_test_se",
			};

			static const struct parent_map gpu_cc_parent_map_1[] = {
			{ P_BI_TCXO, 0 },
			{ P_GPU_CC_PLL0_2X_DIV_CLK_SRC, 1 },
			{ P_GPU_CC_PLL0_OUT_AUX2, 2 },
			{ P_GPU_CC_PLL1_OUT_AUX, 3 },
			{ P_GPU_CC_PLL1_OUT_AUX2, 4 },
			{ P_GPLL0_OUT_MAIN, 5 },
			{ P_CORE_BI_PLL_TEST_SE, 7 },
			};

			static const char * const gpu_cc_parent_names_1[] = {
			"bi_tcxo",
			"gpu_cc_pll0_out_aux",
			"gpu_cc_pll0_out_aux2",
			"gpu_cc_pll1_out_aux",
			"gpu_cc_pll1_out_aux2",
			"gpll0_out_main",
			"core_bi_pll_test_se",
			};

			static struct pll_vco default_vco[] = {
			{ 1000000000, 2000000000, 0 },
			{ 750000000, 1500000000, 1 },
			{ 500000000, 1000000000, 2 },
			{ 250000000, 500000000, 3 },
			};

			static const struct alpha_pll_config gpu_cc_pll0_config = {
			.l = 0x1B,
			.alpha = 0x55000000,
			.alpha_hi = 0xB5,
			.alpha_en_mask = BIT(24),
			.main_output_mask = BIT(0),
			.aux_output_mask = BIT(1),
			.aux2_output_mask = BIT(2),
			.config_ctl_val = 0x40008529,
			};

			/* 532MHz configuration */
			static struct clk_alpha_pll gpu_cc_pll0 = {
			.offset = 0x0,
			.vco_table = default_vco,
			.num_vco = ARRAY_SIZE(default_vco),
			.flags = SUPPORTS_DYNAMIC_UPDATE,
			.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
			.clkr = {
			.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_pll0",
			.parent_names = (const char *[]){ "bi_tcxo" },
			.num_parents = 1,
			.ops = &clk_alpha_pll_ops,
			.vdd_class = &vdd_cx,
			.num_rate_max = VDD_NUM,
			.rate_max = (unsigned long[VDD_NUM]) {
			[VDD_MIN] = 1000000000,
			[VDD_NOMINAL] = 2000000000},
			},
			},
			};

			static const struct clk_div_table post_div_table_gpu_cc_pll0_out_aux2[] = {
			{ 0x0, 1 },
			{ }
			};

			static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_aux2 = {
			.offset = 0x0,
			.post_div_shift = 8,
			.post_div_table = post_div_table_gpu_cc_pll0_out_aux2,
			.num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_aux2),
			.width = 4,
			.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
			.clkr.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_pll0_out_aux2",
			.parent_names = (const char *[]){ "gpu_cc_pll0" },
			.num_parents = 1,
			.flags = CLK_SET_RATE_PARENT,
			.ops = &clk_alpha_pll_postdiv_ops,
			},
			};

			/* 640MHz configuration */
			static const struct alpha_pll_config gpu_cc_pll1_config = {
			.l = 0x21,
			.alpha = 0x55555555,
			.alpha_hi = 0x55,
			.alpha_en_mask = BIT(24),
			.vco_val = 0x2 << 20,
			.vco_mask = GENMASK(21, 20),
			.main_output_mask = BIT(0),
			.aux_output_mask = BIT(1),
			.config_ctl_val = 0x40008529,
			};

			static struct clk_alpha_pll gpu_cc_pll1 = {
			.offset = 0x100,
			.vco_table = default_vco,
			.num_vco = ARRAY_SIZE(default_vco),
			.flags = SUPPORTS_DYNAMIC_UPDATE,
			.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
			.clkr = {
			.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_pll1",
			.parent_names = (const char *[]){ "bi_tcxo" },
			.num_parents = 1,
			.ops = &clk_alpha_pll_ops,
			.vdd_class = &vdd_cx,
			.num_rate_max = VDD_NUM,
			.rate_max = (unsigned long[VDD_NUM]) {
			[VDD_MIN] = 1000000000,
			[VDD_NOMINAL] = 2000000000},
			},
			},
			};

			static const struct clk_div_table post_div_table_gpu_cc_pll1_out_aux[] = {
			{ 0x0, 1 },
			{ }
			};

			static struct clk_alpha_pll_postdiv gpu_cc_pll1_out_aux = {
			.offset = 0x100,
			.post_div_shift = 15,
			.post_div_table = post_div_table_gpu_cc_pll1_out_aux,
			.num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll1_out_aux),
			.width = 3,
			.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
			.clkr.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_pll1_out_aux",
			.parent_names = (const char *[]){ "gpu_cc_pll1" },
			.num_parents = 1,
			.flags = CLK_SET_RATE_PARENT,
			.ops = &clk_alpha_pll_postdiv_ops,
			},
			};

			static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
			F(200000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
			{ }
			};

			static struct clk_rcg2 gpu_cc_gmu_clk_src = {
			.cmd_rcgr = 0x1120,
			.mnd_width = 0,
			.hid_width = 5,
			.parent_map = gpu_cc_parent_map_0,
			.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
			.enable_safe_config = true,
			.clkr.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_gmu_clk_src",
			.parent_names = gpu_cc_parent_names_0,
			.num_parents = 6,
			.flags = CLK_SET_RATE_PARENT,
			.ops = &clk_rcg2_ops,
			.vdd_class = &vdd_cx,
			.num_rate_max = VDD_NUM,
			.rate_max = (unsigned long[VDD_NUM]) {
			[VDD_LOWER] = 200000000},
			},
			};

			static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
			F(320000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0),
			F(465000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0),
			F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
			F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
			F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
			F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
			F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
			F(980000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
			{ }
			};

			static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
			.cmd_rcgr = 0x101c,
			.mnd_width = 0,
			.hid_width = 5,
			.parent_map = gpu_cc_parent_map_1,
			.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
			.clkr.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_gx_gfx3d_clk_src",
			.parent_names = gpu_cc_parent_names_1,
			.num_parents = 7,
			.flags = CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
			.ops = &clk_rcg2_ops,
			.vdd_class = &vdd_cx,
			.num_rate_max = VDD_NUM,
			.rate_max = (unsigned long[VDD_NUM]) {
			[VDD_LOWER] = 320000000,
			[VDD_LOW] = 465000000,
			[VDD_LOW_L1] = 600000000,
			[VDD_NOMINAL] = 745000000,
			[VDD_NOMINAL_L1] = 820000000,
			[VDD_HIGH] = 900000000,
			[VDD_HIGH_L1] = 980000000},
			},
			};

			static struct clk_branch gpu_cc_ahb_clk = {
			.halt_reg = 0x1078,
			.halt_check = BRANCH_HALT_DELAY,
			.clkr = {
			.enable_reg = 0x1078,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_ahb_clk",
			.flags = CLK_IS_CRITICAL,
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch gpu_cc_crc_ahb_clk = {
			.halt_reg = 0x107c,
			.halt_check = BRANCH_HALT_DELAY,
			.clkr = {
			.enable_reg = 0x107c,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_crc_ahb_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch gpu_cc_cx_gfx3d_clk = {
			.halt_reg = 0x10a4,
			.halt_check = BRANCH_HALT_DELAY,
			.clkr = {
			.enable_reg = 0x10a4,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_cx_gfx3d_clk",
			.parent_names = (const char *[]){
			"gpu_cc_gx_gfx3d_clk_src",
			},
			.num_parents = 1,
			.flags = CLK_SET_RATE_PARENT,
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch gpu_cc_cx_gmu_clk = {
			.halt_reg = 0x1098,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0x1098,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_cx_gmu_clk",
			.parent_names = (const char *[]){
			"gpu_cc_gmu_clk_src",
			},
			.num_parents = 1,
			.flags = CLK_SET_RATE_PARENT,
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
			.halt_reg = 0x108c,
			.halt_check = BRANCH_HALT_DELAY,
			.clkr = {
			.enable_reg = 0x108c,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_cx_snoc_dvm_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch gpu_cc_cxo_aon_clk = {
			.halt_reg = 0x1004,
			.halt_check = BRANCH_HALT_DELAY,
			.clkr = {
			.enable_reg = 0x1004,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_cxo_aon_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch gpu_cc_cxo_clk = {
			.halt_reg = 0x109c,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0x109c,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_cxo_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch gpu_cc_gx_cxo_clk = {
			.halt_reg = 0x1060,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0x1060,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_gx_cxo_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch gpu_cc_gx_gfx3d_clk = {
			.halt_reg = 0x1054,
			.halt_check = BRANCH_HALT_SKIP,
			.clkr = {
			.enable_reg = 0x1054,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_gx_gfx3d_clk",
			.parent_names = (const char *[]){
			"gpu_cc_gx_gfx3d_clk_src",
			},
			.num_parents = 1,
			.flags = CLK_SET_RATE_PARENT,
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch gpu_cc_sleep_clk = {
			.halt_reg = 0x1090,
			.halt_check = BRANCH_HALT_DELAY,
			.clkr = {
			.enable_reg = 0x1090,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_sleep_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
			.halt_reg = 0x5000,
			.halt_check = BRANCH_VOTED,
			.clkr = {
			.enable_reg = 0x5000,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_regmap *gpu_cc_bengal_clocks[] = {
			[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
			[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
			[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
			[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
			[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
			[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
			[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
			[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
			[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
			[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
			[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
			[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
			[GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr,
			[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
			[GPU_CC_PLL1_OUT_AUX] = &gpu_cc_pll1_out_aux.clkr,
			[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
			[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
			};

			static const struct regmap_config gpu_cc_bengal_regmap_config = {
			.reg_bits = 32,
			.reg_stride = 4,
			.val_bits = 32,
			.max_register = 0x7008,
			.fast_io = true,
			};

			static const struct qcom_cc_desc gpu_cc_bengal_desc = {
			.config = &gpu_cc_bengal_regmap_config,
			.clks = gpu_cc_bengal_clocks,
			.num_clks = ARRAY_SIZE(gpu_cc_bengal_clocks),
			};

			static const struct of_device_id gpucc_bengal_match_table[] = {
			{ .compatible = "qcom,bengal-gpucc" },
			{ }
			};
			MODULE_DEVICE_TABLE(of, gpucc_bengal_match_table);

			static int gpucc_bengal_probe(struct platform_device *pdev)
			{
			struct regmap *regmap;
			unsigned int value, mask;
			int ret;

			vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
			if (IS_ERR(vdd_cx.regulator[0])) {
			if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER))
			dev_err(&pdev->dev,
			"Unable to get vdd_cx regulator\n");
			return PTR_ERR(vdd_cx.regulator[0]);
			}

			regmap = qcom_cc_map(pdev, &gpu_cc_bengal_desc);
			if (IS_ERR(regmap))
			return PTR_ERR(regmap);

			clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
			clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);

			/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
			mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
			mask \|= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
			value = 0xf << CX_GMU_CBCR_WAKE_SHIFT \| 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
			regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg,
			mask, value);

			ret = qcom_cc_really_probe(pdev, &gpu_cc_bengal_desc, regmap);
			if (ret) {
			dev_err(&pdev->dev, "Failed to register GPUCC clocks\n");
			return ret;
			}

			dev_info(&pdev->dev, "Registered GPUCC clocks\n");
			return ret;
			}

			static struct platform_driver gpucc_bengal_driver = {
			.probe = gpucc_bengal_probe,
			.driver = {
			.name = "bengal-gpucc",
			.of_match_table = gpucc_bengal_match_table,
			},
			};

			static int __init gpu_cc_bengal_init(void)
			{
			return platform_driver_register(&gpucc_bengal_driver);
			}
			subsys_initcall(gpu_cc_bengal_init);

			static void __exit gpu_cc_bengal_exit(void)
			{
			platform_driver_unregister(&gpucc_bengal_driver);
			}
			module_exit(gpu_cc_bengal_exit);

			MODULE_DESCRIPTION("QTI GPU_CC BENGAL Driver");
			MODULE_LICENSE("GPL v2");