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Commit 61c11341 authored by Andi Kleen's avatar Andi Kleen Committed by Linus Torvalds
Browse files

[PATCH] x86-64: Remove esr disable hack in APIC code 



This was just needed for the Numasaurus, which fortunately
doesn't support x86-64 CPUs.

Signed-off-by: default avatarAndi Kleen <ak@suse.de>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent eddfb4ed

arch/x86_64/kernel/apic.c

+1 −20
Original line number Diff line number Diff line
@@ -325,14 +325,6 @@ void __cpuinit setup_local_APIC (void) 
{

	unsigned int value, ver, maxlvt;



	/* Pound the ESR really hard over the head with a big hammer - mbligh */

	if (esr_disable) {

		apic_write(APIC_ESR, 0);

		apic_write(APIC_ESR, 0);

		apic_write(APIC_ESR, 0);

		apic_write(APIC_ESR, 0);

	}



	value = apic_read(APIC_LVR);

	ver = GET_APIC_VERSION(value);
@@ -434,7 +426,7 @@ void __cpuinit setup_local_APIC (void) 
		value |= APIC_LVT_LEVEL_TRIGGER;

	apic_write_around(APIC_LVT1, value);



	if (APIC_INTEGRATED(ver) && !esr_disable) {		/* !82489DX */

	{

		unsigned oldvalue;

		maxlvt = get_maxlvt();

		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
@@ -452,17 +444,6 @@ void __cpuinit setup_local_APIC (void) 
			apic_printk(APIC_VERBOSE,

			"ESR value after enabling vector: %08x, after %08x\n",

			oldvalue, value);

	} else {

		if (esr_disable)	

			/* 

			 * Something untraceble is creating bad interrupts on 

			 * secondary quads ... for the moment, just leave the

			 * ESR disabled - we can't do anything useful with the

			 * errors anyway - mbligh

			 */

			apic_printk(APIC_DEBUG, "Leaving ESR disabled.\n");

		else 

			apic_printk(APIC_DEBUG, "No ESR for 82489DX.\n");

	}



	nmi_watchdog_default();

include/asm-x86_64/apic.h

+0 −1
Original line number Diff line number Diff line
@@ -111,7 +111,6 @@ extern unsigned int nmi_watchdog; 


#endif /* CONFIG_X86_LOCAL_APIC */



#define esr_disable 0

extern unsigned boot_cpu_id;



#endif /* __ASM_APIC_H */