Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 61843f0e authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Name the IPS_PCODE_CONTROL bit 



Give a name to the bit which tells pcode to control IPS.

v2: Note that IPS_CTL bits apply to DISPLAY_IPS_CONTROL as well (Chris)

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170912153411.20171-2-ville.syrjala@linux.intel.com


Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 3e8ddd9e

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -7974,6 +7974,8 @@ enum { 
#define   GEN6_PCODE_WRITE_D_COMP		0x11

#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17

#define   DISPLAY_IPS_CONTROL			0x19

            /* See also IPS_CTL */

#define     IPS_PCODE_CONTROL			(1 << 30)

#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A

#define   GEN9_PCODE_SAGV_CONTROL		0x21

#define     GEN9_SAGV_DISABLE			0x0

drivers/gpu/drm/i915/intel_display.c

+2 −1
Original line number Diff line number Diff line
@@ -4956,7 +4956,8 @@ void hsw_enable_ips(struct intel_crtc *crtc) 
	assert_plane_enabled(dev_priv, crtc->plane);

	if (IS_BROADWELL(dev_priv)) {

		mutex_lock(&dev_priv->rps.hw_lock);

		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));

		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,

						IPS_ENABLE | IPS_PCODE_CONTROL));

		mutex_unlock(&dev_priv->rps.hw_lock);

		/* Quoting Art Runyan: "its not safe to expect any particular

		 * value in IPS_CTL bit 31 after enabling IPS through the