Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 616847e7 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Parametrize ILK turbo registers 



Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4d110c71

drivers/gpu/drm/i915/i915_reg.h

+5 −5
Original line number Diff line number Diff line
@@ -2579,7 +2579,7 @@ enum skl_disp_power_wells { 
#define   TSFS_INTR_MASK	0x000000ff



#define CRSTANDVID		0x11100

#define PXVFREQ_BASE		0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */

#define PXVFREQ(i)		(0x11110 + (i) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */

#define   PXVFREQ_PX_MASK	0x7f000000

#define   PXVFREQ_PX_SHIFT	24

#define VIDFREQ_BASE		0x11110
@@ -2763,8 +2763,8 @@ enum skl_disp_power_wells { 
#define CSIEW0			0x11250

#define CSIEW1			0x11254

#define CSIEW2			0x11258

#define PEW			0x1125c

#define DEW			0x11270

#define PEW(i)			(0x1125c + (i) * 4) /* 5 registers */

#define DEW(i)			(0x11270 + (i) * 4) /* 3 registers */

#define MCHAFE			0x112c0

#define CSIEC			0x112e0

#define DMIEC			0x112e4
@@ -2788,8 +2788,8 @@ enum skl_disp_power_wells { 
#define EG5			0x11624

#define EG6			0x11628

#define EG7			0x1162c

#define PXW			0x11664

#define PXWL			0x11680

#define PXW(i)			(0x11664 + (i) * 4) /* 4 registers */

#define PXWL(i)			(0x11680 + (i) * 4) /* 8 registers */

#define LCFUSE02		0x116c0

#define   LCFUSE_HIV_MASK	0x000000ff

#define CSIPLL0			0x12c10

drivers/gpu/drm/i915/intel_pm.c

+7 −7
Original line number Diff line number Diff line
@@ -4282,7 +4282,7 @@ static void ironlake_enable_drps(struct drm_device *dev) 
	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>

		MEMMODE_FSTART_SHIFT;



	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>

	vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>

		PXVFREQ_PX_SHIFT;



	dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
@@ -5915,7 +5915,7 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) 


	assert_spin_locked(&mchdev_lock);



	pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));

	pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));

	pxvid = (pxvid >> 24) & 0x7f;

	ext_v = pvid_to_extvid(dev_priv, pxvid);
@@ -6158,13 +6158,13 @@ static void intel_init_emon(struct drm_device *dev) 
	I915_WRITE(CSIEW2, 0x04000004);



	for (i = 0; i < 5; i++)

		I915_WRITE(PEW + (i * 4), 0);

		I915_WRITE(PEW(i), 0);

	for (i = 0; i < 3; i++)

		I915_WRITE(DEW + (i * 4), 0);

		I915_WRITE(DEW(i), 0);



	/* Program P-state weights to account for frequency power adjustment */

	for (i = 0; i < 16; i++) {

		u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));

		u32 pxvidfreq = I915_READ(PXVFREQ(i));

		unsigned long freq = intel_pxfreq(pxvidfreq);

		unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>

			PXVFREQ_PX_SHIFT;
@@ -6185,7 +6185,7 @@ static void intel_init_emon(struct drm_device *dev) 
	for (i = 0; i < 4; i++) {

		u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |

			(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);

		I915_WRITE(PXW + (i * 4), val);

		I915_WRITE(PXW(i), val);

	}



	/* Adjust magic regs to magic values (more experimental results) */
@@ -6201,7 +6201,7 @@ static void intel_init_emon(struct drm_device *dev) 
	I915_WRITE(EG7, 0);



	for (i = 0; i < 8; i++)

		I915_WRITE(PXWL + (i * 4), 0);

		I915_WRITE(PXWL(i), 0);



	/* Enable PMON + select events */

	I915_WRITE(ECR, 0x80000019);