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Commit 6157f257 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: Add cdiv clocks for gcc, video and camera cc driver for KONA"

parents 06070a23 c88b8062

drivers/clk/qcom/camcc-kona.c

+18 −3
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2018, The Linux Foundation. All rights reserved.*/

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.*/



#define pr_fmt(fmt) "clk: %s: " fmt, __func__
@@ -22,6 +22,7 @@ 
#include "clk-pll.h"

#include "clk-rcg.h"

#include "clk-regmap.h"

#include "clk-regmap-divider.h"

#include "common.h"

#include "reset.h"

#include "vdd-level.h"
@@ -437,6 +438,18 @@ static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 
	},

};



static struct clk_regmap_div cam_cc_sbi_div_clk_src = {

	.reg = 0x9010,

	.shift = 0,

	.width = 3,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "cam_cc_sbi_div_clk_src",

		.parent_names = (const char *[]){ "cam_cc_ife_0_clk_src" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};



static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
@@ -1179,6 +1192,7 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 
	.hid_width = 5,

	.parent_map = cam_cc_parent_map_0,

	.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_slow_ahb_clk_src",

		.parent_names = cam_cc_parent_names_0,
@@ -1358,7 +1372,7 @@ static struct clk_branch cam_cc_cci_1_clk = { 


static struct clk_branch cam_cc_core_ahb_clk = {

	.halt_reg = 0xc150,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0xc150,

		.enable_mask = BIT(0),
@@ -2301,7 +2315,7 @@ static struct clk_branch cam_cc_sbi_clk = { 
		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_sbi_clk",

			.parent_names = (const char *[]){

				"cam_cc_ife_0_clk_src",

				"cam_cc_sbi_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -2505,6 +2519,7 @@ static struct clk_regmap *cam_cc_kona_clocks[] = { 
	[CAM_CC_SBI_CPHY_RX_CLK] = &cam_cc_sbi_cphy_rx_clk.clkr,

	[CAM_CC_SBI_CSID_CLK] = &cam_cc_sbi_csid_clk.clkr,

	[CAM_CC_SBI_CSID_CLK_SRC] = &cam_cc_sbi_csid_clk_src.clkr,

	[CAM_CC_SBI_DIV_CLK_SRC] = &cam_cc_sbi_div_clk_src.clkr,

	[CAM_CC_SBI_IFE_0_CLK] = &cam_cc_sbi_ife_0_clk.clkr,

	[CAM_CC_SBI_IFE_1_CLK] = &cam_cc_sbi_ife_1_clk.clkr,

	[CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,

drivers/clk/qcom/clk-rcg.h

+3 −3
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */

/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2013, 2018-2019, The Linux Foundation. All rights reserved. */



#ifndef __QCOM_CLK_RCG_H__

#define __QCOM_CLK_RCG_H__
@@ -179,7 +179,7 @@ struct clk_rcg_dfs_data { 
};



#define DEFINE_RCG_DFS(r) \

	{ .rcg = &r##_src, .init = &r##_init }

	{ .rcg = &r, .init = &r##_init }



extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,

				    const struct clk_rcg_dfs_data *rcgs,

drivers/clk/qcom/gcc-kona.c

+188 −140

File changed.

Preview size limit exceeded, changes collapsed.

drivers/clk/qcom/videocc-kona.c

+68 −45
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 */

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.*/



#define pr_fmt(fmt) "clk: %s: " fmt, __func__
@@ -24,12 +22,11 @@ 
#include "clk-pll.h"

#include "clk-rcg.h"

#include "clk-regmap.h"

#include "clk-regmap-divider.h"

#include "common.h"

#include "reset.h"

#include "vdd-level.h"



#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }



static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);
@@ -157,6 +154,54 @@ static struct clk_alpha_pll video_pll1 = { 
	},

};



static struct clk_regmap_div video_cc_mvs0_div_clk_src = {

	.reg = 0xd54,

	.shift = 0,

	.width = 2,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "video_cc_mvs0_div_clk_src",

		.parent_names = (const char *[]){ "video_cc_mvs0_clk_src" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};



static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {

	.reg = 0xc54,

	.shift = 0,

	.width = 2,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "video_cc_mvs0c_div2_div_clk_src",

		.parent_names = (const char *[]){ "video_cc_mvs0_clk_src" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};



static struct clk_regmap_div video_cc_mvs1_div_clk_src = {

	.reg = 0xdd4,

	.shift = 0,

	.width = 2,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "video_cc_mvs1_div_clk_src",

		.parent_names = (const char *[]){ "video_cc_mvs1_clk_src" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};



static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {

	.reg = 0xcf4,

	.shift = 0,

	.width = 2,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "video_cc_mvs1c_div2_div_clk_src",

		.parent_names = (const char *[]){ "video_cc_mvs1_clk_src" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};



static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	{ }
@@ -304,19 +349,6 @@ static struct clk_branch video_cc_ahb_clk = { 
	},

};



static struct clk_branch video_cc_debug_clk = {

	.halt_reg = 0xebc,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0xebc,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "video_cc_debug_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch video_cc_mvs0_clk = {

	.halt_reg = 0xd34,

	.halt_check = BRANCH_HALT_VOTED,
@@ -326,7 +358,7 @@ static struct clk_branch video_cc_mvs0_clk = { 
		.hw.init = &(struct clk_init_data){

			.name = "video_cc_mvs0_clk",

			.parent_names = (const char *[]){

				"video_cc_mvs0_clk_src",

				"video_cc_mvs0_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -344,7 +376,7 @@ static struct clk_branch video_cc_mvs0c_clk = { 
		.hw.init = &(struct clk_init_data){

			.name = "video_cc_mvs0c_clk",

			.parent_names = (const char *[]){

				"video_cc_mvs0_clk_src",

				"video_cc_mvs0c_div2_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -362,7 +394,7 @@ static struct clk_branch video_cc_mvs1_clk = { 
		.hw.init = &(struct clk_init_data){

			.name = "video_cc_mvs1_clk",

			.parent_names = (const char *[]){

				"video_cc_mvs1_clk_src",

				"video_cc_mvs1_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -380,7 +412,7 @@ static struct clk_branch video_cc_mvs1_div2_clk = { 
		.hw.init = &(struct clk_init_data){

			.name = "video_cc_mvs1_div2_clk",

			.parent_names = (const char *[]){

				"video_cc_mvs1_clk_src",

				"video_cc_mvs1c_div2_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -398,7 +430,7 @@ static struct clk_branch video_cc_mvs1c_clk = { 
		.hw.init = &(struct clk_init_data){

			.name = "video_cc_mvs1c_clk",

			.parent_names = (const char *[]){

				"video_cc_mvs1_clk_src",

				"video_cc_mvs1c_div2_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -407,19 +439,6 @@ static struct clk_branch video_cc_mvs1c_clk = { 
	},

};



static struct clk_branch video_cc_pll_test_clk = {

	.halt_reg = 0xec8,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0xec8,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "video_cc_pll_test_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch video_cc_sleep_clk = {

	.halt_reg = 0xf10,

	.halt_check = BRANCH_HALT,
@@ -459,15 +478,19 @@ static struct clk_branch video_cc_xo_clk = { 
static struct clk_regmap *video_cc_kona_clocks[] = {

	[VIDEO_CC_AHB_CLK] = &video_cc_ahb_clk.clkr,

	[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,

	[VIDEO_CC_DEBUG_CLK] = &video_cc_debug_clk.clkr,

	[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,

	[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,

	[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,

	[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,

	[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] =

		&video_cc_mvs0c_div2_div_clk_src.clkr,

	[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,

	[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,

	[VIDEO_CC_MVS1_DIV2_CLK] = &video_cc_mvs1_div2_clk.clkr,

	[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,

	[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,

	[VIDEO_CC_PLL_TEST_CLK] = &video_cc_pll_test_clk.clkr,

	[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] =

		&video_cc_mvs1c_div2_div_clk_src.clkr,

	[VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,

	[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,

	[VIDEO_CC_XO_CLK] = &video_cc_xo_clk.clkr,
@@ -479,11 +502,11 @@ static struct clk_regmap *video_cc_kona_clocks[] = { 
static const struct qcom_reset_map video_cc_kona_resets[] = {

	[CVP_VIDEO_CC_INTERFACE_BCR] = { 0xe54 },

	[CVP_VIDEO_CC_MVS0_BCR] = { 0xd14 },

	[VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },

	[CVP_VIDEO_CC_MVS0C_BCR] = { 0xbf4 },

	[CVP_VIDEO_CC_MVS1_BCR] = { 0xd94 },

	[VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },

	[CVP_VIDEO_CC_MVS1C_BCR] = { 0xc94 },

	[VIDEO_CC_MVS0C_CLK_BCR] = { 0xc34, 2},

	[VIDEO_CC_MVS1C_CLK_BCR] = { 0xcd4, 2},

};



static const struct regmap_config video_cc_kona_regmap_config = {

include/dt-bindings/clock/qcom,camcc-kona.h

+10 −14
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */



#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_KONA_H

#define _DT_BINDINGS_CLK_QCOM_CAM_CC_KONA_H



/* CAM_CC clocks */

#define CAM_CC_BPS_AHB_CLK					0

#define CAM_CC_BPS_AREG_CLK					1

#define CAM_CC_BPS_AXI_CLK					2
@@ -108,20 +109,15 @@ 
#define CAM_CC_SBI_CPHY_RX_CLK					101

#define CAM_CC_SBI_CSID_CLK					102

#define CAM_CC_SBI_CSID_CLK_SRC					103

#define CAM_CC_SBI_IFE_0_CLK					104

#define CAM_CC_SBI_IFE_1_CLK					105

#define CAM_CC_SLEEP_CLK					106

#define CAM_CC_SLEEP_CLK_SRC					107

#define CAM_CC_SLOW_AHB_CLK_SRC					108

#define CAM_CC_XO_CLK_SRC					109



#define BPS_GDSC						0

#define IFE_0_GDSC						1

#define IFE_1_GDSC						2

#define IPE_0_GDSC						3

#define SBI_GDSC						4

#define TITAN_TOP_GDSC						5

#define CAM_CC_SBI_DIV_CLK_SRC					104

#define CAM_CC_SBI_IFE_0_CLK					105

#define CAM_CC_SBI_IFE_1_CLK					106

#define CAM_CC_SLEEP_CLK					107

#define CAM_CC_SLEEP_CLK_SRC					108

#define CAM_CC_SLOW_AHB_CLK_SRC					109

#define CAM_CC_XO_CLK_SRC					110



/* CAM_CC resets */

#define CAM_CC_BPS_BCR						0

#define CAM_CC_ICP_BCR						1

#define CAM_CC_IFE_0_BCR					2