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Commit 604c307b authored by Joerg Roedel's avatar Joerg Roedel
Browse files

Merge branches 'dma-debug/next', 'amd-iommu/command-cleanups', 'amd-iommu/ats'... 

Merge branches 'dma-debug/next', 'amd-iommu/command-cleanups', 'amd-iommu/ats' and 'amd-iommu/extended-features' into iommu/2.6.40

Conflicts:
	arch/x86/include/asm/amd_iommu_types.h
	arch/x86/kernel/amd_iommu.c
	arch/x86/kernel/amd_iommu_init.c
parents e9696875 ba4b87ad fd7b5535 58fc7f14

arch/x86/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -690,6 +690,7 @@ config AMD_IOMMU 
	bool "AMD IOMMU support"

	select SWIOTLB

	select PCI_MSI

	select PCI_IOV

	depends on X86_64 && PCI && ACPI

	---help---

	  With this option you can enable support for AMD IOMMU hardware in

arch/x86/include/asm/amd_iommu_proto.h

+9 −3
Original line number Diff line number Diff line
@@ -19,13 +19,11 @@ 
#ifndef _ASM_X86_AMD_IOMMU_PROTO_H

#define _ASM_X86_AMD_IOMMU_PROTO_H



struct amd_iommu;

#include <asm/amd_iommu_types.h>



extern int amd_iommu_init_dma_ops(void);

extern int amd_iommu_init_passthrough(void);

extern irqreturn_t amd_iommu_int_handler(int irq, void *data);

extern void amd_iommu_flush_all_domains(void);

extern void amd_iommu_flush_all_devices(void);

extern void amd_iommu_apply_erratum_63(u16 devid);

extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu);

extern int amd_iommu_init_devices(void);
@@ -44,4 +42,12 @@ static inline bool is_rd890_iommu(struct pci_dev *pdev) 
	       (pdev->device == PCI_DEVICE_ID_RD890_IOMMU);

}



static inline bool iommu_feature(struct amd_iommu *iommu, u64 f)

{

	if (!(iommu->cap & (1 << IOMMU_CAP_EFR)))

		return false;



	return !!(iommu->features & f);

}



#endif /* _ASM_X86_AMD_IOMMU_PROTO_H  */

arch/x86/include/asm/amd_iommu_types.h

+24 −4
Original line number Diff line number Diff line
@@ -68,12 +68,25 @@ 
#define MMIO_CONTROL_OFFSET     0x0018

#define MMIO_EXCL_BASE_OFFSET   0x0020

#define MMIO_EXCL_LIMIT_OFFSET  0x0028

#define MMIO_EXT_FEATURES	0x0030

#define MMIO_CMD_HEAD_OFFSET	0x2000

#define MMIO_CMD_TAIL_OFFSET	0x2008

#define MMIO_EVT_HEAD_OFFSET	0x2010

#define MMIO_EVT_TAIL_OFFSET	0x2018

#define MMIO_STATUS_OFFSET	0x2020





/* Extended Feature Bits */

#define FEATURE_PREFETCH	(1ULL<<0)

#define FEATURE_PPR		(1ULL<<1)

#define FEATURE_X2APIC		(1ULL<<2)

#define FEATURE_NX		(1ULL<<3)

#define FEATURE_GT		(1ULL<<4)

#define FEATURE_IA		(1ULL<<6)

#define FEATURE_GA		(1ULL<<7)

#define FEATURE_HE		(1ULL<<8)

#define FEATURE_PC		(1ULL<<9)



/* MMIO status bits */

#define MMIO_STATUS_COM_WAIT_INT_MASK	0x04
@@ -114,6 +127,8 @@ 
#define CMD_COMPL_WAIT          0x01

#define CMD_INV_DEV_ENTRY       0x02

#define CMD_INV_IOMMU_PAGES	0x03

#define CMD_INV_IOTLB_PAGES	0x04

#define CMD_INV_ALL		0x08



#define CMD_COMPL_WAIT_STORE_MASK	0x01

#define CMD_COMPL_WAIT_INT_MASK		0x02
@@ -215,6 +230,8 @@ 
#define IOMMU_PTE_IR (1ULL << 61)

#define IOMMU_PTE_IW (1ULL << 62)



#define DTE_FLAG_IOTLB	0x01



#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)

#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)

#define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
@@ -227,6 +244,7 @@ 
/* IOMMU capabilities */

#define IOMMU_CAP_IOTLB   24

#define IOMMU_CAP_NPCACHE 26

#define IOMMU_CAP_EFR     27



#define MAX_DOMAIN_ID 65536
@@ -249,6 +267,8 @@ extern bool amd_iommu_dump; 


/* global flag if IOMMUs cache non-present entries */

extern bool amd_iommu_np_cache;

/* Only true if all IOMMUs support device IOTLBs */

extern bool amd_iommu_iotlb_sup;



/*

 * Make iterating over all IOMMUs easier
@@ -371,6 +391,9 @@ struct amd_iommu { 
	/* flags read from acpi table */

	u8 acpi_flags;



	/* Extended features */

	u64 features;



	/*

	 * Capability pointer. There could be more than one IOMMU per PCI

	 * device function if there are more than one AMD IOMMU capability
@@ -409,9 +432,6 @@ struct amd_iommu { 
	/* if one, we need to send a completion wait command */

	bool need_sync;



	/* becomes true if a command buffer reset is running */

	bool reset_in_progress;



	/* default dma_ops domain for that IOMMU */

	struct dma_ops_domain *default_dom;

arch/x86/kernel/amd_iommu.c

+302 −217

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arch/x86/kernel/amd_iommu_init.c

+35 −4

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