Loading drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c +2 −1 Original line number Original line Diff line number Diff line Loading @@ -413,7 +413,8 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; csiphy_dev->is_divisor_32_comp = false; csiphy_dev->is_divisor_32_comp = false; csiphy_dev->clk_lane = 0; csiphy_dev->clk_lane = 0; csiphy_dev->ctrl_reg->data_rates_settings_table = NULL; csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_2_0; } else { } else { CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x", CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x", csiphy_dev->hw_version); csiphy_dev->hw_version); Loading drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h +26 −0 Original line number Original line Diff line number Diff line Loading @@ -291,4 +291,30 @@ struct csiphy_reg_t csiphy_3ph_v2_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { }, }, }; }; struct data_rate_settings_t data_rate_delta_table_2_0 = { .num_data_rate_settings = 2, .data_rate_settings = { { /* (2 * 10**9 * 2.28) rounded value*/ .bandwidth = 4560000000, .data_rate_reg_array_size = 3, .csiphy_data_rate_regs = { {0x164, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x364, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x564, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, } }, { /* (2.5 * 10**9 * 2.28) rounded value*/ .bandwidth = 5700000000, .data_rate_reg_array_size = 3, .csiphy_data_rate_regs = { {0x164, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x364, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x564, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, } }, } }; #endif /* _CAM_CSIPHY_2_0_HWREG_H_ */ #endif /* _CAM_CSIPHY_2_0_HWREG_H_ */ Loading
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c +2 −1 Original line number Original line Diff line number Diff line Loading @@ -413,7 +413,8 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; csiphy_dev->is_divisor_32_comp = false; csiphy_dev->is_divisor_32_comp = false; csiphy_dev->clk_lane = 0; csiphy_dev->clk_lane = 0; csiphy_dev->ctrl_reg->data_rates_settings_table = NULL; csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_2_0; } else { } else { CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x", CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x", csiphy_dev->hw_version); csiphy_dev->hw_version); Loading
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h +26 −0 Original line number Original line Diff line number Diff line Loading @@ -291,4 +291,30 @@ struct csiphy_reg_t csiphy_3ph_v2_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { }, }, }; }; struct data_rate_settings_t data_rate_delta_table_2_0 = { .num_data_rate_settings = 2, .data_rate_settings = { { /* (2 * 10**9 * 2.28) rounded value*/ .bandwidth = 4560000000, .data_rate_reg_array_size = 3, .csiphy_data_rate_regs = { {0x164, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x364, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x564, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, } }, { /* (2.5 * 10**9 * 2.28) rounded value*/ .bandwidth = 5700000000, .data_rate_reg_array_size = 3, .csiphy_data_rate_regs = { {0x164, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x364, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x564, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, } }, } }; #endif /* _CAM_CSIPHY_2_0_HWREG_H_ */ #endif /* _CAM_CSIPHY_2_0_HWREG_H_ */