Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6039b80e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-4.8-rc1' of git://git.infradead.org/users/vkoul/slave-dma 

Pull dmaengine updates from Vinod Koul:
 "This time we have bit of largish changes: two new drivers, bunch of
  updates and cleanups to existing set.  Nothing super exciting though.

  New drivers:
   - Xilinx zynqmp dma engine driver
   - Marvell xor2 driver

  Updates:
   - dmatest sg support
   - updates and enhancements to Xilinx drivers, adding of cyclic mode
   - clock handling fixes across drivers
   - removal of OOM messages on kzalloc across subsystem
   - interleaved transfers support in omap driver
   - runtime pm support in qcom bam dma
   - tasklet kill freeup across drivers
   - irq cleanup on remove across drivers"

* tag 'dmaengine-4.8-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (94 commits)
  dmaengine: k3dma: add missing clk_disable_unprepare() on error in k3_dma_probe()
  dmaengine: zynqmp_dma: add missing MODULE_LICENSE
  dmaengine: qcom_hidma: use for_each_matching_node() macro
  dmaengine: zynqmp_dma: Fix static checker warning
  dmaengine: omap-dma: Support for interleaved transfer
  dmaengine: ioat: statify symbol
  dmaengine: pxa_dma: implement device_synchronize
  dmaengine: imx-sdma: remove assignment never used
  dmaengine: imx-sdma: remove dummy assignment
  dmaengine: cppi: remove unused and bogus check
  dmaengine: qcom_hidma_lli: kill the tasklets upon exit
  dmaengine: pxa_dma: remove owner assignment
  dmaengine: fsl_raid: remove owner assignment
  dmaengine: coh901318: remove owner assignment
  dmaengine: qcom_hidma: kill the tasklets upon exit
  dmaengine: txx9dmac: explicitly freeup irq
  dmaengine: sirf-dma: kill the tasklets upon exit
  dmaengine: s3c24xx: kill the tasklets upon exit
  dmaengine: s3c24xx: explicitly freeup irq
  dmaengine: pl330: explicitly freeup irq
  ...
parents c9b011a8 4bb04396

Documentation/devicetree/bindings/dma/mv-xor-v2.txt

0 → 100644
+24 −0
Original line number Diff line number Diff line 
* Marvell XOR v2 engines



Required properties:

- compatible: one of the following values:

    "marvell,armada-7k-xor"

    "marvell,xor-v2"

- reg: Should contain registers location and length (two sets)

    the first set is the DMA registers

    the second set is the global registers

- msi-parent: Phandle to the MSI-capable interrupt controller used for

  interrupts.



Optional properties:

- clocks: Optional reference to the clock used by the XOR engine.



Example:



	xor0@400000 {

		compatible = "marvell,xor-v2";

		reg = <0x400000 0x1000>,

		      <0x410000 0x1000>;

		msi-parent = <&gic_v2m0>;

		dma-coherent;

	};

Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt

+72 −22
Original line number Diff line number Diff line 
Xilinx AXI VDMA engine, it does transfers between memory and video devices.

It can be configured to have one channel or two channels. If configured

as two channels, one is to transmit to the video device and another is

to receive from the video device.



Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream

target devices. It can be configured to have one channel or two channels.

If configured as two channels, one is to transmit to the device and another

is to receive from the device.



Xilinx AXI CDMA engine, it does transfers between memory-mapped source

address and a memory-mapped destination address.



Required properties:

- compatible: Should be "xlnx,axi-dma-1.00.a"

- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or

	      "xlnx,axi-cdma-1.00.a""

- #dma-cells: Should be <1>, see "dmas" property below

- reg: Should contain DMA registers location and length.

- reg: Should contain VDMA registers location and length.

- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).

- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.

- dma-channel child node: Should have at least one channel and can have up to

	two channels per device. This node specifies the properties of each

	DMA channel (see child node properties below).

- clocks: Input clock specifier. Refer to common clock bindings.

- clock-names: List of input clocks

	For VDMA:

	Required elements: "s_axi_lite_aclk"

	Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",

			   "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"

	For CDMA:

	Required elements: "s_axi_lite_aclk", "m_axi_aclk"

	FOR AXIDMA:

	Required elements: "s_axi_lite_aclk"

	Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",

			   "m_axi_sg_aclk"



Required properties for VDMA:

- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.



Optional properties:

- xlnx,include-sg: Tells whether configured for Scatter-mode in

- xlnx,include-sg: Tells configured for Scatter-mode in

	the hardware.

Optional properties for AXI DMA:

- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.

Optional properties for VDMA:

- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.

	It takes following values:

	{1}, flush both channels

	{2}, flush mm2s channel

	{3}, flush s2mm channel



Required child node properties:

- compatible: It should be either "xlnx,axi-dma-mm2s-channel" or

- compatible:

	For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or

	"xlnx,axi-vdma-s2mm-channel".

	For CDMA: It should be "xlnx,axi-cdma-channel".

	For AXIDMA: It should be either "xlnx,axi-dma-mm2s-channel" or

	"xlnx,axi-dma-s2mm-channel".

- interrupts: Should contain per channel DMA interrupts.

- interrupts: Should contain per channel VDMA interrupts.

- xlnx,datawidth: Should contain the stream data width, take values

	{32,64...1024}.



Option child node properties:

- xlnx,include-dre: Tells whether hardware is configured for Data

Optional child node properties:

- xlnx,include-dre: Tells hardware is configured for Data

	Realignment Engine.

Optional child node properties for VDMA:

- xlnx,genlock-mode: Tells Genlock synchronization is

	enabled/disabled in hardware.

Optional child node properties for AXI DMA:

-dma-channels: Number of dma channels in child node.



Example:

++++++++



axi_dma_0: axidma@40400000 {

	compatible = "xlnx,axi-dma-1.00.a";

axi_vdma_0: axivdma@40030000 {

	compatible = "xlnx,axi-vdma-1.00.a";

	#dma_cells = <1>;

	reg = < 0x40400000 0x10000 >;

	dma-channel@40400000 {

		compatible = "xlnx,axi-dma-mm2s-channel";

		interrupts = < 0 59 4 >;

	reg = < 0x40030000 0x10000 >;

	dma-ranges = <0x00000000 0x00000000 0x40000000>;

	xlnx,num-fstores = <0x8>;

	xlnx,flush-fsync = <0x1>;

	xlnx,addrwidth = <0x20>;

	clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;

	clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",

		      "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";

	dma-channel@40030000 {

		compatible = "xlnx,axi-vdma-mm2s-channel";

		interrupts = < 0 54 4 >;

		xlnx,datawidth = <0x40>;

	} ;

	dma-channel@40400030 {

		compatible = "xlnx,axi-dma-s2mm-channel";

		interrupts = < 0 58 4 >;

	dma-channel@40030030 {

		compatible = "xlnx,axi-vdma-s2mm-channel";

		interrupts = < 0 53 4 >;

		xlnx,datawidth = <0x40>;

	} ;

} ;
@@ -49,7 +99,7 @@ axi_dma_0: axidma@40400000 { 
* DMA client



Required properties:

- dmas: a list of <[DMA device phandle] [Channel ID]> pairs,

- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,

	where Channel ID is '0' for write/tx and '1' for read/rx

	channel.

- dma-names: a list of DMA channel names, one per "dmas" entry
@@ -57,9 +107,9 @@ Required properties: 
Example:

++++++++



dmatest_0: dmatest@0 {

	compatible ="xlnx,axi-dma-test-1.00.a";

	dmas = <&axi_dma_0 0

		&axi_dma_0 1>;

	dma-names = "dma0", "dma1";

vdmatest_0: vdmatest@0 {

	compatible ="xlnx,axi-vdma-test-1.00.a";

	dmas = <&axi_vdma_0 0

		&axi_vdma_0 1>;

	dma-names = "vdma0", "vdma1";

} ;

Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt

deleted100644 → 0
+0 −107
Original line number Diff line number Diff line 
Xilinx AXI VDMA engine, it does transfers between memory and video devices.

It can be configured to have one channel or two channels. If configured

as two channels, one is to transmit to the video device and another is

to receive from the video device.



Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream

target devices. It can be configured to have one channel or two channels.

If configured as two channels, one is to transmit to the device and another

is to receive from the device.



Xilinx AXI CDMA engine, it does transfers between memory-mapped source

address and a memory-mapped destination address.



Required properties:

- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or

	      "xlnx,axi-cdma-1.00.a""

- #dma-cells: Should be <1>, see "dmas" property below

- reg: Should contain VDMA registers location and length.

- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).

- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.

- dma-channel child node: Should have at least one channel and can have up to

	two channels per device. This node specifies the properties of each

	DMA channel (see child node properties below).

- clocks: Input clock specifier. Refer to common clock bindings.

- clock-names: List of input clocks

	For VDMA:

	Required elements: "s_axi_lite_aclk"

	Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",

			   "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"

	For CDMA:

	Required elements: "s_axi_lite_aclk", "m_axi_aclk"

	FOR AXIDMA:

	Required elements: "s_axi_lite_aclk"

	Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",

			   "m_axi_sg_aclk"



Required properties for VDMA:

- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.



Optional properties:

- xlnx,include-sg: Tells configured for Scatter-mode in

	the hardware.

Optional properties for VDMA:

- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.

	It takes following values:

	{1}, flush both channels

	{2}, flush mm2s channel

	{3}, flush s2mm channel



Required child node properties:

- compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or

	"xlnx,axi-vdma-s2mm-channel".

- interrupts: Should contain per channel VDMA interrupts.

- xlnx,datawidth: Should contain the stream data width, take values

	{32,64...1024}.



Optional child node properties:

- xlnx,include-dre: Tells hardware is configured for Data

	Realignment Engine.

Optional child node properties for VDMA:

- xlnx,genlock-mode: Tells Genlock synchronization is

	enabled/disabled in hardware.



Example:

++++++++



axi_vdma_0: axivdma@40030000 {

	compatible = "xlnx,axi-vdma-1.00.a";

	#dma_cells = <1>;

	reg = < 0x40030000 0x10000 >;

	dma-ranges = <0x00000000 0x00000000 0x40000000>;

	xlnx,num-fstores = <0x8>;

	xlnx,flush-fsync = <0x1>;

	xlnx,addrwidth = <0x20>;

	clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;

	clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",

		      "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";

	dma-channel@40030000 {

		compatible = "xlnx,axi-vdma-mm2s-channel";

		interrupts = < 0 54 4 >;

		xlnx,datawidth = <0x40>;

	} ;

	dma-channel@40030030 {

		compatible = "xlnx,axi-vdma-s2mm-channel";

		interrupts = < 0 53 4 >;

		xlnx,datawidth = <0x40>;

	} ;

} ;





* DMA client



Required properties:

- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,

	where Channel ID is '0' for write/tx and '1' for read/rx

	channel.

- dma-names: a list of DMA channel names, one per "dmas" entry



Example:

++++++++



vdmatest_0: vdmatest@0 {

	compatible ="xlnx,axi-vdma-test-1.00.a";

	dmas = <&axi_vdma_0 0

		&axi_vdma_0 1>;

	dma-names = "vdma0", "vdma1";

} ;

Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt

0 → 100644
+27 −0
Original line number Diff line number Diff line 
Xilinx ZynqMP DMA engine, it does support memory to memory transfers,

memory to device and device to memory transfers. It also has flow

control and rate control support for slave/peripheral dma access.



Required properties:

- compatible		: Should be "xlnx,zynqmp-dma-1.0"

- reg			: Memory map for gdma/adma module access.

- interrupt-parent	: Interrupt controller the interrupt is routed through

- interrupts		: Should contain DMA channel interrupt.

- xlnx,bus-width	: Axi buswidth in bits. Should contain 128 or 64

- clock-names		: List of input clocks "clk_main", "clk_apb"

			  (see clock bindings for details)



Optional properties:

- dma-coherent		: Present if dma operations are coherent.



Example:

++++++++

fpd_dma_chan1: dma@fd500000 {

	compatible = "xlnx,zynqmp-dma-1.0";

	reg = <0x0 0xFD500000 0x1000>;

	interrupt-parent = <&gic>;

	interrupts = <0 117 4>;

	clock-names = "clk_main", "clk_apb";

	xlnx,bus-width = <128>;

	dma-coherent;

};

drivers/dma/Kconfig

+29 −3
Original line number Diff line number Diff line
@@ -339,6 +339,20 @@ config MV_XOR 
	---help---

	  Enable support for the Marvell XOR engine.



config MV_XOR_V2

	bool "Marvell XOR engine version 2 support "

	depends on ARM64

	select DMA_ENGINE

	select DMA_ENGINE_RAID

	select ASYNC_TX_ENABLE_CHANNEL_SWITCH

	select GENERIC_MSI_IRQ_DOMAIN

	---help---

	  Enable support for the Marvell version 2 XOR engine.



	  This engine provides acceleration for copy, XOR and RAID6

	  operations, and is available on Marvell Armada 7K and 8K

	  platforms.



config MXS_DMA

	bool "MXS DMA support"

	depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q || SOC_IMX6UL
@@ -519,19 +533,31 @@ config XGENE_DMA 
	help

	  Enable support for the APM X-Gene SoC DMA engine.



config XILINX_VDMA

	tristate "Xilinx AXI VDMA Engine"

config XILINX_DMA

	tristate "Xilinx AXI DMAS Engine"

	depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)

	select DMA_ENGINE

	help

	  Enable support for Xilinx AXI VDMA Soft IP.



	  This engine provides high-bandwidth direct memory access

	  AXI VDMA engine provides high-bandwidth direct memory access

	  between memory and AXI4-Stream video type target

	  peripherals including peripherals which support AXI4-

	  Stream Video Protocol.  It has two stream interfaces/

	  channels, Memory Mapped to Stream (MM2S) and Stream to

	  Memory Mapped (S2MM) for the data transfers.

	  AXI CDMA engine provides high-bandwidth direct memory access

	  between a memory-mapped source address and a memory-mapped

	  destination address.

	  AXI DMA engine provides high-bandwidth one dimensional direct

	  memory access between memory and AXI4-Stream target peripherals.



config XILINX_ZYNQMP_DMA

	tristate "Xilinx ZynqMP DMA Engine"

	depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)

	select DMA_ENGINE

	help

	  Enable support for Xilinx ZynqMP DMA controller.



config ZX_DMA

	tristate "ZTE ZX296702 DMA support"