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Commit 601109c5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2017-02-17' of... 

Merge tag 'drm-intel-next-fixes-2017-02-17' of git://anongit.freedesktop.org/git/drm-intel into drm-next

i915 and GVT fixes for v4.11 merge window

* tag 'drm-intel-next-fixes-2017-02-17' of git://anongit.freedesktop.org/git/drm-intel: (32 commits)
  drm/i915: Fix not finding the VBT when it overlaps with OPREGION_ASLE_EXT
  drm/i915: Pass timeout==0 on to i915_gem_object_wait_fence()
  drm/i915/gvt: Disable access to stolen memory as a guest
  drm/i915: Avoid spurious WARNs about the wrong pipe in the PPS code
  drm/i915: Check for timeout completion when waiting for the rq to submitted
  drm/i915: A hotfix for making aliasing PPGTT work for GVT-g
  drm/i915: Restore context and pd for ringbuffer submission after reset
  drm/i915: Let execlist_update_context() cover !FULL_PPGTT mode.
  drm/i915/lspcon: Fix resume time initialization due to unasserted HPD
  drm/i915/gen9+: Enable hotplug detection early
  drm/i915: Reject set-tiling-ioctl with stride==0 and a tiling mode
  drm/i915: Recreate internal objects with single page segments if dmar fails
  drm/i915/gvt: return error code if dma map iova failed
  drm/i915/gvt: optimize the inhibit context mmio load
  drm/i915/gvt: add sprite plane flip done support.
  drm/i915/gvt: add missing display part reset for vGPU reset
  drm/i915/gvt: Fix shadow context descriptor
  drm/i915/gvt: Fix alignment for GTT allocation
  drm/i915/gvt: fix crash at function release_shadow_wa_ctx
  drm/i915/gvt: enable IOMMU for gvt
  ...
parents 8fd4a62d 998d7573

drivers/gpu/drm/i915/gvt/aperture_gm.c

+8 −7
Original line number Diff line number Diff line
@@ -49,20 +49,21 @@ static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm) 
	if (high_gm) {

		node = &vgpu->gm.high_gm_node;

		size = vgpu_hidden_sz(vgpu);

		start = gvt_hidden_gmadr_base(gvt);

		end = gvt_hidden_gmadr_end(gvt);

		start = ALIGN(gvt_hidden_gmadr_base(gvt), I915_GTT_PAGE_SIZE);

		end = ALIGN(gvt_hidden_gmadr_end(gvt), I915_GTT_PAGE_SIZE);

		flags = PIN_HIGH;

	} else {

		node = &vgpu->gm.low_gm_node;

		size = vgpu_aperture_sz(vgpu);

		start = gvt_aperture_gmadr_base(gvt);

		end = gvt_aperture_gmadr_end(gvt);

		start = ALIGN(gvt_aperture_gmadr_base(gvt), I915_GTT_PAGE_SIZE);

		end = ALIGN(gvt_aperture_gmadr_end(gvt), I915_GTT_PAGE_SIZE);

		flags = PIN_MAPPABLE;

	}



	mutex_lock(&dev_priv->drm.struct_mutex);

	ret = i915_gem_gtt_insert(&dev_priv->ggtt.base, node,

				  size, 4096, I915_COLOR_UNEVICTABLE,

				  size, I915_GTT_PAGE_SIZE,

				  I915_COLOR_UNEVICTABLE,

				  start, end, flags);

	mutex_unlock(&dev_priv->drm.struct_mutex);

	if (ret)
@@ -254,7 +255,7 @@ static int alloc_resource(struct intel_vgpu *vgpu, 
	if (request > avail)

		goto no_enough_resource;



	vgpu_aperture_sz(vgpu) = request;

	vgpu_aperture_sz(vgpu) = ALIGN(request, I915_GTT_PAGE_SIZE);



	item = "high GM space";

	max = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
@@ -265,7 +266,7 @@ static int alloc_resource(struct intel_vgpu *vgpu, 
	if (request > avail)

		goto no_enough_resource;



	vgpu_hidden_sz(vgpu) = request;

	vgpu_hidden_sz(vgpu) = ALIGN(request, I915_GTT_PAGE_SIZE);



	item = "fence";

	max = gvt_fence_sz(gvt) - HOST_FENCE;

drivers/gpu/drm/i915/gvt/cmd_parser.c

+19 −1
Original line number Diff line number Diff line
@@ -1135,6 +1135,8 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, 
	u32 dword2 = cmd_val(s, 2);

	u32 plane = (dword0 & GENMASK(12, 8)) >> 8;



	info->plane = PRIMARY_PLANE;



	switch (plane) {

	case MI_DISPLAY_FLIP_SKL_PLANE_1_A:

		info->pipe = PIPE_A;
@@ -1148,12 +1150,28 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, 
		info->pipe = PIPE_C;

		info->event = PRIMARY_C_FLIP_DONE;

		break;



	case MI_DISPLAY_FLIP_SKL_PLANE_2_A:

		info->pipe = PIPE_A;

		info->event = SPRITE_A_FLIP_DONE;

		info->plane = SPRITE_PLANE;

		break;

	case MI_DISPLAY_FLIP_SKL_PLANE_2_B:

		info->pipe = PIPE_B;

		info->event = SPRITE_B_FLIP_DONE;

		info->plane = SPRITE_PLANE;

		break;

	case MI_DISPLAY_FLIP_SKL_PLANE_2_C:

		info->pipe = PIPE_C;

		info->event = SPRITE_C_FLIP_DONE;

		info->plane = SPRITE_PLANE;

		break;



	default:

		gvt_err("unknown plane code %d\n", plane);

		return -EINVAL;

	}



	info->pipe = PRIMARY_PLANE;

	info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;

	info->tile_val = (dword1 & GENMASK(2, 0));

	info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;

drivers/gpu/drm/i915/gvt/display.c

+24 −7
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 
	return 0;

}



/* EDID with 1024x768 as its resolution */

/* EDID with 1920x1200 as its resolution */

static unsigned char virtual_dp_monitor_edid[] = {

	/*Header*/

	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
@@ -97,11 +97,16 @@ static unsigned char virtual_dp_monitor_edid[] = { 
	0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,

	/* Established Timings: maximum resolution is 1024x768 */

	0x21, 0x08, 0x00,

	/* Standard Timings. All invalid */

	0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,

	0x00, 0x40, 0x00, 0x00, 0x00, 0x01,

	/* 18 Byte Data Blocks 1: invalid */

	0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,

	/*

	 * Standard Timings.

	 * below new resolutions can be supported:

	 * 1920x1080, 1280x720, 1280x960, 1280x1024,

	 * 1440x900, 1600x1200, 1680x1050

	 */

	0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,

	0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,

	/* 18 Byte Data Blocks 1: max resolution is 1920x1200 */

	0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,

	0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,

	/* 18 Byte Data Blocks 2: invalid */

	0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
@@ -115,7 +120,7 @@ static unsigned char virtual_dp_monitor_edid[] = { 
	/* Extension Block Count */

	0x00,

	/* Checksum */

	0xef,

	0x45,

};



#define DPCD_HEADER_SIZE        0xb
@@ -328,3 +333,15 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu) 
	else

		return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B);

}



/**

 * intel_vgpu_reset_display- reset vGPU virtual display emulation

 * @vgpu: a vGPU

 *

 * This function is used to reset vGPU virtual display emulation stuffs

 *

 */

void intel_vgpu_reset_display(struct intel_vgpu *vgpu)

{

	emulate_monitor_status_change(vgpu);

}

drivers/gpu/drm/i915/gvt/display.h

+1 −0
Original line number Diff line number Diff line
@@ -158,6 +158,7 @@ void intel_gvt_emulate_vblank(struct intel_gvt *gvt); 
void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt);



int intel_vgpu_init_display(struct intel_vgpu *vgpu);

void intel_vgpu_reset_display(struct intel_vgpu *vgpu);

void intel_vgpu_clean_display(struct intel_vgpu *vgpu);



#endif

drivers/gpu/drm/i915/gvt/execlist.c

+1 −1
Original line number Diff line number Diff line
@@ -515,7 +515,7 @@ static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload) 


static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)

{

	if (wa_ctx->indirect_ctx.size == 0)

	if (!wa_ctx->indirect_ctx.obj)

		return;



	i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);