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Commit 5ff04a84 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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MIPS: define bits introduced for hybrid FPRs 



Add definitions for the FRE & UFE bits in Config5, and the FREP bit in
FPIR. These bits are used to support a hybrid FPR scheme allowing a
mixture of FP32 & FP64 code to execute within a task.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Alexander Viro <viro@zeniv.linux.org.uk>
Cc: linux-fsdevel@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7674/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 774c105e

arch/mips/include/asm/mipsregs.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -653,6 +653,8 @@ 
#define MIPS_CONF5_NF		(_ULCAST_(1) << 0)

#define MIPS_CONF5_NF		(_ULCAST_(1) << 0)

#define MIPS_CONF5_UFR		(_ULCAST_(1) << 2)

#define MIPS_CONF5_UFR		(_ULCAST_(1) << 2)

#define MIPS_CONF5_MRP		(_ULCAST_(1) << 3)

#define MIPS_CONF5_MRP		(_ULCAST_(1) << 3)

#define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)

#define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)

#define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)

#define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)

#define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)

#define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)

#define MIPS_CONF5_CV		(_ULCAST_(1) << 29)

#define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
@@ -692,6 +694,7 @@ 
#define MIPS_FPIR_W		(_ULCAST_(1) << 20)

#define MIPS_FPIR_W		(_ULCAST_(1) << 20)

#define MIPS_FPIR_L		(_ULCAST_(1) << 21)

#define MIPS_FPIR_L		(_ULCAST_(1) << 21)

#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)

#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)

#define MIPS_FPIR_FREP		(_ULCAST_(1) << 29)





/*

/*

 * Bits in the MIPS32 Memory Segmentation registers.

 * Bits in the MIPS32 Memory Segmentation registers.