Commit 5fd2a84a authored May 09, 2011 by Avinash H.M Committed by Tony Lindgren May 13, 2011

OMAP3: set the core dpll clk rate in its set_rate function

The debug l3_ick/rate is not displaying the actual rate of the clock in
hardware. This is because, the core dpll set_rate function doesn't update the
clk.rate. After fixing, the l3_ick/rate is displaying proper values.

Signed-off-by: Shweta Gulati <shweta.gulati@ti.com>
Signed-off-by: Avinash.H.M <avinashhm@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Wamsley <paul@pwsan.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

parent c56b2ddd

arch/arm/mach-omap2/clkt34xx_dpll3m2.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -115,6 +115,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
		sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
		sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
		0, 0, 0, 0);
		clk->rate = rate;

		return 0;
		}