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Commit 5fb6fdaf authored by John Youn's avatar John Youn Committed by Felipe Balbi
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usb: dwc3: gadget: Fix dead code writing GCTL.RAMCLKSEL 



The register programming code in dwc2_updated_ram_clk_sel() will never
be executed. And in fact the entire function can be removed as there is
no way to override the default value of GCTL.RAMCLKSEL. Remove the
function and add a comment explaining where GCTL.RAMCLKSEL should be
programmed if needed in the future.

This fixes dead code warnings in coverity.

Signed-off-by: default avatarJohn Youn <johnyoun@synopsys.com>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent 3c220370

drivers/usb/dwc3/gadget.c

+8 −27
Original line number Original line Diff line number Diff line
@@ -2468,32 +2468,6 @@ static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 
	dwc3_writel(dwc->regs, DWC3_DCFG, reg);

	dwc3_writel(dwc->regs, DWC3_DCFG, reg);

}

}





static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)

{

	u32 reg;

	u32 usb30_clock = DWC3_GCTL_CLK_BUS;



	/*

	 * We change the clock only at SS but I dunno why I would want to do

	 * this. Maybe it becomes part of the power saving plan.

	 */



	if ((speed != DWC3_DSTS_SUPERSPEED) &&

	    (speed != DWC3_DSTS_SUPERSPEED_PLUS))

		return;



	/*

	 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed

	 * each time on Connect Done.

	 */

	if (!usb30_clock)

		return;



	reg = dwc3_readl(dwc->regs, DWC3_GCTL);

	reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);

	dwc3_writel(dwc->regs, DWC3_GCTL, reg);

}



static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)

static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)

{

{

	struct dwc3_ep		*dep;

	struct dwc3_ep		*dep;
@@ -2505,7 +2479,14 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 
	speed = reg & DWC3_DSTS_CONNECTSPD;

	speed = reg & DWC3_DSTS_CONNECTSPD;

	dwc->speed = speed;

	dwc->speed = speed;





	dwc3_update_ram_clk_sel(dwc, speed);

	/*

	 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed

	 * each time on Connect Done.

	 *

	 * Currently we always use the reset value. If any platform

	 * wants to set this to a different value, we need to add a

	 * setting and update GCTL.RAMCLKSEL here.

	 */





	switch (speed) {

	switch (speed) {

	case DWC3_DSTS_SUPERSPEED_PLUS:

	case DWC3_DSTS_SUPERSPEED_PLUS: