Merge "msm: kgsl: Specify bus width in gpucore structure" (5f235cf5) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/gpu/msm/adreno-gpulist.h

+20 −0

Original line number	Diff line number	Diff line
		@@ -29,6 +29,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306 = {
		.gmem_base = 0,
		.gmem_size = SZ_128K,
		.busy_mask = 0x7ffffffe,
		.bus_width = 0,
		},
		.pm4fw_name = "a300_pm4.fw",
		.pfpfw_name = "a300_pfp.fw",
		@@ -50,6 +51,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306a = {
		.gmem_base = 0,
		.gmem_size = SZ_128K,
		.busy_mask = 0x7ffffffe,
		.bus_width = 16,
		},
		.pm4fw_name = "a300_pm4.fw",
		.pfpfw_name = "a300_pfp.fw",
		@@ -69,6 +71,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a304 = {
		.gmem_base = 0,
		.gmem_size = (SZ_64K + SZ_32K),
		.busy_mask = 0x7ffffffe,
		.bus_width = 0,
		},
		.pm4fw_name = "a300_pm4.fw",
		.pfpfw_name = "a300_pfp.fw",
		@@ -193,6 +196,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = {
		.gmem_size = SZ_1M,
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.gpmu_tsens = 0x00060007,
		.max_power = 5448,
		@@ -218,6 +222,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = {
		.gmem_size = SZ_1M,
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.gpmu_tsens = 0x00060007,
		.max_power = 5448,
		@@ -283,6 +288,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a505 = {
		.gmem_size = (SZ_128K + SZ_8K),
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 16,
		},
		.pm4fw_name = "a530_pm4.fw",
		.pfpfw_name = "a530_pfp.fw",
		@@ -302,6 +308,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = {
		.gmem_size = (SZ_128K + SZ_8K),
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 16,
		},
		.pm4fw_name = "a530_pm4.fw",
		.pfpfw_name = "a530_pfp.fw",
		@@ -379,6 +386,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a510 = {
		.gmem_size = SZ_256K,
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 16,
		},
		.pm4fw_name = "a530_pm4.fw",
		.pfpfw_name = "a530_pfp.fw",
		@@ -504,6 +512,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = {
		.gmem_size = SZ_1M,
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.gpmu_tsens = 0x000c000d,
		.max_power = 5448,
		@@ -586,6 +595,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a512 = {
		.gmem_size = (SZ_256K + SZ_16K),
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.pm4fw_name = "a530_pm4.fw",
		.pfpfw_name = "a530_pfp.fw",
		@@ -604,6 +614,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = {
		.gmem_size = (SZ_128K + SZ_8K),
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.pm4fw_name = "a530_pm4.fw",
		.pfpfw_name = "a530_pfp.fw",
		@@ -740,6 +751,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = {
		.gmem_size = SZ_1M,
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.prim_fifo_threshold = 0x0018000,
		.pdc_address_offset = 0x00030080,
		@@ -837,6 +849,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = {
		.gmem_size = SZ_512K,
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.prim_fifo_threshold = 0x0018000,
		.pdc_address_offset = 0x00030080,
		@@ -862,6 +875,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = {
		.gmem_size = SZ_512K,
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.prim_fifo_threshold = 0x0018000,
		.pdc_address_offset = 0x00030090,
		@@ -948,6 +962,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = {
		.gmem_size = SZ_512K,
		.num_protected_regs = 0x30,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.prim_fifo_threshold = 0x0010000,
		.pdc_address_offset = 0x000300a0,
		@@ -1035,6 +1050,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = {
		.gmem_size = SZ_1M, //Verified 1MB
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.prim_fifo_threshold = 0x00200000,
		.pdc_address_offset = 0x00030090,
		@@ -1112,6 +1128,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = {
		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */
		.num_protected_regs = 0x30,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.prim_fifo_threshold = 0x00300000,
		.pdc_address_offset = 0x000300A0,
		@@ -1134,6 +1151,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = {
		.gmem_size = SZ_2M,
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.prim_fifo_threshold = 0x00400000,
		.pdc_address_offset = 0x00030090,
		@@ -1208,6 +1226,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = {
		.gmem_size = (SZ_128K + SZ_4K),
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.prim_fifo_threshold = 0x00080000,
		.pdc_address_offset = 0x00030080,
		@@ -1231,6 +1250,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = {
		.gmem_size = SZ_512K,
		.num_protected_regs = 0x20,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		},
		.prim_fifo_threshold = 0x0018000,
		.pdc_address_offset = 0x00030080,

drivers/gpu/msm/adreno.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -1361,6 +1361,8 @@ static int adreno_probe(struct platform_device *pdev)
		if (adreno_support_64bit(adreno_dev))
		device->mmu.features \|= KGSL_MMU_64BIT;

		device->pwrctrl.bus_width = adreno_dev->gpucore->bus_width;

		status = kgsl_device_platform_probe(device);
		if (status) {
		device->pdev = NULL;

drivers/gpu/msm/adreno.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -354,6 +354,7 @@ struct adreno_reglist {
		* @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core
		* @num_protected_regs: number of protected registers
		* @busy_mask: mask to check if GPU is busy in RBBM_STATUS
		* @bus_width: Bytes transferred in 1 cycle
		*/
		struct adreno_gpu_core {
		enum adreno_gpurev gpurev;
		@@ -364,6 +365,7 @@ struct adreno_gpu_core {
		size_t gmem_size;
		unsigned int num_protected_regs;
		unsigned int busy_mask;
		u32 bus_width;
		};

		enum gpu_coresight_sources {

drivers/gpu/msm/kgsl_pwrctrl.c

+0 −5

Original line number	Diff line number	Diff line
		@@ -2101,11 +2101,6 @@ int kgsl_pwrctrl_init(struct kgsl_device *device)

		pm_runtime_enable(&pdev->dev);

		/* Bus width in bytes, set it to zero if not found */
		if (of_property_read_u32(pdev->dev.of_node, "qcom,bus-width",
		&pwr->bus_width))
		pwr->bus_width = 0;

		/* Check if gpu bandwidth vote device is defined in dts */
		if (pwr->bus_control)
		/* Check if gpu bandwidth vote device is defined in dts */