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Commit 5f077839 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add support for dummy clocks for Lagoon"

parents 27f25697 1bf2141e

qcom/lagoon-gdsc.dtsi

0 → 100644
+150 −0
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&soc {

	/* GDSCs in GCC */

	gcc_pcie_0_gdsc: qcom,gdsc@14e004 {

		compatible = "regulator-fixed";

		reg = <0x14e004 0x4>;

		regulator-name = "gcc_pcie_0_gdsc";

		status = "disabled";

	};



	gcc_ufs_phy_gdsc: qcom,gdsc@13a004 {

		compatible = "regulator-fixed";

		reg = <0x13a004 0x4>;

		regulator-name = "gcc_ufs_phy_gdsc";

		status = "disabled";

	};



	gcc_usb30_prim_gdsc: qcom,gdsc@11a004 {

		compatible = "regulator-fixed";

		reg = <0x11a004 0x4>;

		regulator-name = "gcc_usb30_prim_gdsc";

		status = "disabled";

	};



	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@1b7040 {

		compatible = "regulator-fixed";

		reg = <0x1b7040 0x4>;

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";

		qcom,no-status-check-on-disable;

		status = "disabled";

	};



	hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@1b7044 {

		compatible = "regulator-fixed";

		reg = <0x1b7044 0x4>;

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";

		qcom,no-status-check-on-disable;

		status = "disabled";

	};



	/* GDSCs in CAMCC */

	cam_cc_bps_gdsc: qcom,gdsc@ad06004 {

		compatible = "regulator-fixed";

		reg = <0xad06004 0x4>;

		regulator-name = "cam_cc_bps_gdsc";

		status = "disabled";

	};



	cam_cc_ife_0_gdsc: qcom,gdsc@ad09004 {

		compatible = "regulator-fixed";

		reg = <0xad09004 0x4>;

		regulator-name = "cam_cc_ife_0_gdsc";

		status = "disabled";

	};



	cam_cc_ife_1_gdsc: qcom,gdsc@ad0a004 {

		compatible = "regulator-fixed";

		reg = <0xad0a004 0x4>;

		regulator-name = "cam_cc_ife_1_gdsc";

		status = "disabled";

	};



	cam_cc_ife_2_gdsc: qcom,gdsc@ad0b004 {

		compatible = "regulator-fixed";

		reg = <0xad0b004 0x4>;

		regulator-name = "cam_cc_ife_2_gdsc";

		status = "disabled";

	};



	cam_cc_ipe_0_gdsc: qcom,gdsc@ad07004 {

		compatible = "regulator-fixed";

		reg = <0xad07004 0x4>;

		regulator-name = "cam_cc_ipe_0_gdsc";

		status = "disabled";

	};



	cam_cc_titan_top_gdsc: qcom,gdsc@ad14004 {

		compatible = "regulator-fixed";

		reg = <0xad14004 0x4>;

		regulator-name = "cam_cc_titan_top_gdsc";

		status = "disabled";

	};



	/* GDSCs in DISPCC */

	mdss_core_gdsc: qcom,gdsc@af01004 {

		compatible = "regulator-fixed";

		reg = <0xaf01004 0x4>;

		regulator-name = "mdss_core_gdsc";

		proxy-supply = <&mdss_core_gdsc>;

		qcom,proxy-consumer-enable;

		status = "disabled";

	};



	/* GDSCs in GPUCC */

	gpu_gx_domain_addr: syscon@3d91508 {

		compatible = "syscon";

		reg = <0x3d91508 0x4>;

	};



	gpu_gx_sw_reset: syscon@3d91008 {

		compatible = "syscon";

		reg = <0x3d91008 0x4>;

	};



	gpu_cx_hw_ctrl: syscon@3d91540 {

		compatible = "syscon";

		reg = <0x3d91540 0x4>;

	};



	gpu_cx_gdsc: qcom,gdsc@3d9106c {

		compatible = "regulator-fixed";

		reg = <0x3d9106c 0x4>;

		regulator-name = "gpu_cx_gdsc";

		hw-ctl-addr = <&gpu_cx_hw_ctrl>;

		qcom,no-status-check-on-disable;

		status = "disabled";

	};



	gpu_gx_gdsc: qcom,gdsc@3d9100c {

		compatible = "regulator-fixed";

		reg = <0x3d9100c 0x4>;

		regulator-name = "gpu_gx_gdsc";

		sw-reset = <&gpu_gx_sw_reset>;

		domain-addr = <&gpu_gx_domain_addr>;

		qcom,reset-aon-logic;

		status = "disabled";

	};



	/* GDSCs in NPUCC */

	npu_cc_core_gdsc: qcom,gdsc@9981004 {

		compatible = "regulator-fixed";

		reg = <0x9981004 0x4>;

		regulator-name = "npu_cc_core_gdsc";

		status = "disabled";

	};



	/* GDSCs in VIDEOCC */

	video_cc_mvs0_gdsc: qcom,gdsc@aaf3004 {

		compatible = "regulator-fixed";

		reg = <0xaaf3004 0x4>;

		regulator-name = "video_cc_mvs0_gdsc";

		status = "disabled";

	};



	video_cc_mvsc_gdsc: qcom,gdsc@aaf2004 {

		compatible = "regulator-fixed";

		reg = <0xaaf2004 0x4>;

		regulator-name = "video_cc_mvsc_gdsc";

		status = "disabled";

	};

};

qcom/lagoon.dtsi

+172 −0
Original line number Diff line number Diff line 
#include <dt-bindings/clock/qcom,aop-qmp.h>

#include <dt-bindings/clock/qcom,camcc-lagoon.h>

#include <dt-bindings/clock/qcom,dispcc-lagoon.h>

#include <dt-bindings/clock/qcom,gcc-lagoon.h>

#include <dt-bindings/clock/qcom,gpucc-lagoon.h>

#include <dt-bindings/clock/qcom,npucc-lagoon.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,videocc-lagoon.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {
@@ -637,6 +645,170 @@ 
			qcom,dump-id = <0x127>;

		};

	};



	clocks {

		xo_board: xo-board {

			compatible = "fixed-clock";

			clock-frequency = <76800000>;

			clock-output-names = "xo_board";

			#clock-cells = <0>;

		};



		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			clock-frequency = <32764>;

			clock-output-names = "sleep_clk";

			#clock-cells = <0>;

		};

	};



	bi_tcxo: bi_tcxo {

		compatible = "fixed-factor-clock";

		clock-mult = <1>;

		clock-div = <4>;

		clocks = <&xo_board>;

		#clock-cells = <0>;

	};



	bi_tcxo_ao: bi_tcxo_ao {

		compatible = "fixed-factor-clock";

		clock-mult = <1>;

		clock-div = <2>;

		clocks = <&xo_board>;

		#clock-cells = <0>;

	};



	aopcc: qcom,aopcc {

		compatible = "qcom,dummycc";

		clock-output-names = "aopcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	rpmhcc: qcom,rpmhcc {

		compatible = "qcom,dummycc";

		clock-output-names = "rpmhcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	gcc: qcom,gcc@100000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	camcc: qcom,camcc@ad00000 {

		compatible = "qcom,dummycc";

		clock-output-names = "camcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	dispcc: qcom,dispcc@af00000 {

		compatible = "qcom,dummycc";

		clock-output-names = "dispcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	gpucc: qcom,gpucc@3d90000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	npucc: qcom,npucc@9980000 {

		compatible = "qcom,dummycc";

		clock-output-names = "npucc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	videocc: qcom,videocc@aaf0000 {

		compatible = "qcom,dummycc";

		clock-output-names = "videocc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

};



#include "lagoon-gdsc.dtsi"



&gcc_pcie_0_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&gcc_ufs_phy_gdsc {

	status = "ok";

};



&gcc_usb30_prim_gdsc {

	status = "ok";

};



&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {

	status = "ok";

};



&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {

	status = "ok";

};



&cam_cc_bps_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&cam_cc_ife_0_gdsc {

	status = "ok";

};



&cam_cc_ife_1_gdsc {

	status = "ok";

};



&cam_cc_ife_2_gdsc {

	status = "ok";

};



&cam_cc_ipe_0_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&cam_cc_titan_top_gdsc {

	status = "ok";

};



&mdss_core_gdsc {

	status = "ok";

};



&gpu_gx_gdsc {

	parent-supply = <&VDD_CX_LEVEL>;

	status = "ok";

};



&gpu_cx_gdsc {

	parent-supply = <&VDD_CX_LEVEL>;

	status = "ok";

};



&npu_cc_core_gdsc {

	status = "ok";

};



&video_cc_mvs0_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&video_cc_mvsc_gdsc {

	status = "ok";

};



#include "lagoon-pinctrl.dtsi"