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Commit 5ecba18f authored by Vipin Deep Kaur's avatar Vipin Deep Kaur Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add QUPV3 SE dt node for spi on lito 

Add initial device tree node for QUPV3 spi instance
on lito.

Change-Id: I39426cff22cb7337d828eb39fccc79caab42782e
parent d9b024ce

qcom/lito-pinctrl.dtsi

+352 −0
Original line number Diff line number Diff line
@@ -1078,5 +1078,357 @@ 
				};

			};

		};



		qupv3_se0_spi_pins: qupv3_se0_spi_pins {

			qupv3_se0_spi_active: qupv3_se0_spi_active {

				mux {

					pins = "gpio42", "gpio43", "gpio44",

								"gpio45";

					function = "qup00";

				};



				config {

					pins = "gpio42", "gpio43", "gpio44",

								"gpio45";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {

				mux {

					pins = "gpio42", "gpio43", "gpio44",

								"gpio45";

					function = "gpio";

				};



				config {

					pins = "gpio42", "gpio43", "gpio44",

								"gpio45";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se1_spi_pins: qupv3_se1_spi_pins {

			qupv3_se1_spi_active: qupv3_se1_spi_active {

				mux {

					pins = "gpio0", "gpio1", "gpio2",

								"gpio3";

					function = "qup01";

				};



				config {

					pins = "gpio0", "gpio1", "gpio2",

								"gpio3";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {

				mux {

					pins = "gpio0", "gpio1", "gpio2",

								"gpio3";

					function = "gpio";

				};



				config {

					pins = "gpio0", "gpio1", "gpio2",

								"gpio3";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se2_spi_pins: qupv3_se2_spi_pins {

			qupv3_se2_spi_active: qupv3_se2_spi_active {

				mux {

					pins = "gpio34", "gpio35", "gpio36",

								"gpio37";

					function = "qup02";

				};



				config {

					pins = "gpio34", "gpio35", "gpio36",

								"gpio37";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {

				mux {

					pins = "gpio34", "gpio35", "gpio36",

								"gpio37";

					function = "gpio";

				};



				config {

					pins = "gpio34", "gpio35", "gpio36",

								"gpio37";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se4_spi_pins: qupv3_se4_spi_pins {

			qupv3_se4_spi_active: qupv3_se4_spi_active {

				mux {

					pins = "gpio31", "gpio32", "gpio29",

								"gpio30";

					function = "qup04";

				};



				config {

					pins = "gpio31", "gpio32", "gpio29",

								"gpio30";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {

				mux {

					pins = "gpio31", "gpio32", "gpio29",

								"gpio30";

					function = "gpio";

				};



				config {

					pins = "gpio31", "gpio32", "gpio29",

								"gpio30";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se5_spi_pins: qupv3_se5_spi_pins {

			qupv3_se5_spi_active: qupv3_se5_spi_active {

				mux {

					pins = "gpio38", "gpio39", "gpio40",

								"gpio41";

					function = "qup05";

				};



				config {

					pins = "gpio38", "gpio39", "gpio40",

								"gpio41";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {

				mux {

					pins = "gpio38", "gpio39", "gpio40",

								"gpio41";

					function = "gpio";

				};



				config {

					pins = "gpio38", "gpio39", "gpio40",

								"gpio41";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se6_spi_pins: qupv3_se6_spi_pins {

			qupv3_se6_spi_active: qupv3_se6_spi_active {

				mux {

					pins = "gpio59", "gpio60", "gpio61",

								"gpio62";

					function = "qup10";

				};



				config {

					pins = "gpio59", "gpio60", "gpio61",

								"gpio62";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {

				mux {

					pins = "gpio59", "gpio60", "gpio61",

								"gpio62";

					function = "gpio";

				};



				config {

					pins = "gpio59", "gpio60", "gpio61",

								"gpio62";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se7_spi_pins: qupv3_se7_spi_pins {

			qupv3_se7_spi_active: qupv3_se7_spi_active {

				mux {

					pins = "gpio6", "gpio7", "gpio8",

								"gpio9";

					function = "qup11";

				};



				config {

					pins = "gpio6", "gpio7", "gpio8",

								"gpio9";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {

				mux {

					pins = "gpio6", "gpio7", "gpio8",

								"gpio9";

					function = "gpio";

				};



				config {

					pins = "gpio6", "gpio7", "gpio8",

								"gpio9";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se8_spi_pins: qupv3_se8_spi_pins {

			qupv3_se8_spi_active: qupv3_se8_spi_active {

				mux {

					pins = "gpio49", "gpio50", "gpio51",

								"gpio52";

					function = "qup12";

				};



				config {

					pins = "gpio49", "gpio50", "gpio51",

								"gpio52";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {

				mux {

					pins = "gpio49", "gpio50", "gpio51",

								"gpio52";

					function = "gpio";

				};



				config {

					pins = "gpio49", "gpio50", "gpio51",

								"gpio52";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se9_spi_pins: qupv3_se9_spi_pins {

			qupv3_se9_spi_active: qupv3_se9_spi_active {

				mux {

					pins = "gpio46", "gpio47", "gpio48",

								"gpio63";

					function = "qup13";

				};



				config {

					pins = "gpio46", "gpio47", "gpio48",

								"gpio63";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {

				mux {

					pins = "gpio46", "gpio47", "gpio48",

								"gpio63";

					function = "gpio";

				};



				config {

					pins = "gpio46", "gpio47", "gpio48",

								"gpio63";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se10_spi_pins: qupv3_se10_spi_pins {

			qupv3_se10_spi_active: qupv3_se10_spi_active {

				mux {

					pins = "gpio53", "gpio54", "gpio55",

								"gpio56";

					function = "qup14";

				};



				config {

					pins = "gpio53", "gpio54", "gpio55",

								"gpio56";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {

				mux {

					pins = "gpio53", "gpio54", "gpio55",

								"gpio56";

					function = "gpio";

				};



				config {

					pins = "gpio53", "gpio54", "gpio55",

								"gpio56";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se11_spi_pins: qupv3_se11_spi_pins {

			qupv3_se11_spi_active: qupv3_se11_spi_active {

				mux {

					pins = "gpio108", "gpio109", "gpio112",

								"gpio113";

					function = "qup15";

				};



				config {

					pins = "gpio108", "gpio109", "gpio112",

								"gpio113";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {

				mux {

					pins = "gpio108", "gpio109", "gpio112",

								"gpio113";

					function = "gpio";

				};



				config {

					pins = "gpio108", "gpio109", "gpio112",

								"gpio113";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};

	};

};

qcom/lito-qupv3.dtsi

+244 −0
Original line number Diff line number Diff line
@@ -177,6 +177,117 @@ 
		status = "disabled";

	};



	/* SPI */

	qupv3_se0_spi: spi@880000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x880000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se0_spi_active>;

		pinctrl-1 = <&qupv3_se0_spi_sleep>;

		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;

		dmas = <&gpi_dma0 0 0 1 64 0>,

			<&gpi_dma0 1 0 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};



	qupv3_se1_spi: spi@884000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x884000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se1_spi_active>;

		pinctrl-1 = <&qupv3_se1_spi_sleep>;

		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;

		dmas = <&gpi_dma0 0 1 1 64 0>,

			<&gpi_dma0 1 1 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};



	qupv3_se2_spi: spi@888000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x888000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se2_spi_active>;

		pinctrl-1 = <&qupv3_se2_spi_sleep>;

		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;

		dmas = <&gpi_dma0 0 2 1 64 0>,

			<&gpi_dma0 1 2 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};



	qupv3_se4_spi: spi@890000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x890000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se4_spi_active>;

		pinctrl-1 = <&qupv3_se4_spi_sleep>;

		interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;

		dmas = <&gpi_dma0 0 4 1 64 0>,

			<&gpi_dma0 1 4 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};



	qupv3_se5_spi: spi@894000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x894000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se5_spi_active>;

		pinctrl-1 = <&qupv3_se5_spi_sleep>;

		interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;

		dmas = <&gpi_dma0 0 5 1 64 0>,

			<&gpi_dma0 1 5 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};



	/* QUPv3 South_1 Instances

	 * South_1 0 : SE 6

	 * South_1 1 : SE 7
@@ -351,4 +462,137 @@ 
		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	/* SPI */

	qupv3_se6_spi: spi@980000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x980000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se6_spi_active>;

		pinctrl-1 = <&qupv3_se6_spi_active>;

		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_1>;

		dmas = <&gpi_dma1 0 0 1 64 0>,

			<&gpi_dma1 1 0 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};



	qupv3_se7_spi: spi@984000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x984000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se7_spi_active>;

		pinctrl-1 = <&qupv3_se7_spi_sleep>;

		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_1>;

		dmas = <&gpi_dma1 0 1 1 64 0>,

			<&gpi_dma1 1 1 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};



	qupv3_se8_spi: spi@988000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x988000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se8_spi_active>;

		pinctrl-1 = <&qupv3_se8_spi_sleep>;

		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_1>;

		dmas = <&gpi_dma1 0 2 1 64 0>,

			<&gpi_dma1 1 2 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};



	qupv3_se9_spi: spi@98c000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x98c000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se9_spi_active>;

		pinctrl-1 = <&qupv3_se9_spi_sleep>;

		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_1>;

		dmas = <&gpi_dma1 0 3 1 64 0>,

			<&gpi_dma1 1 3 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};



	qupv3_se10_spi: spi@990000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x990000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se10_spi_active>;

		pinctrl-1 = <&qupv3_se10_spi_sleep>;

		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_1>;

		dmas = <&gpi_dma1 0 4 1 64 0>,

			<&gpi_dma1 1 4 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};



	qupv3_se11_spi: spi@994000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x994000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se11_spi_active>;

		pinctrl-1 = <&qupv3_se11_spi_sleep>;

		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_1>;

		dmas = <&gpi_dma1 0 5 1 64 0>,

			<&gpi_dma1 1 5 1 64 0>;

		dma-names = "tx", "rx";

		status = "disabled";

	};

};