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Commit 5e84e1a4 authored by Zhenyu Wang's avatar Zhenyu Wang Committed by Chris Wilson
Browse files

drm/i915: Fix KMS regression on Sandybridge/CPT 



We should enable FDI normal training on Sandybridge/CPT system
as well.

Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
[ickle: removed unrelated chunks]
Cc: stable@kernel.org
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 48fcfc88

drivers/gpu/drm/i915/intel_display.c

+33 −21
Original line number Diff line number Diff line
@@ -1681,6 +1681,37 @@ static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) 
	udelay(500);

}



static void intel_fdi_normal_train(struct drm_crtc *crtc)

{

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_crtc->pipe;

	u32 reg, temp;



	/* enable normal train */

	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~FDI_LINK_TRAIN_NONE;

	temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;

	I915_WRITE(reg, temp);



	reg = FDI_RX_CTL(pipe);

	temp = I915_READ(reg);

	if (HAS_PCH_CPT(dev)) {

		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

		temp |= FDI_LINK_TRAIN_NORMAL_CPT;

	} else {

		temp &= ~FDI_LINK_TRAIN_NONE;

		temp |= FDI_LINK_TRAIN_NONE;

	}

	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);



	/* wait one idle pattern time */

	POSTING_READ(reg);

	udelay(1000);

}



/* The FDI link training functions for ILK/Ibexpeak. */

static void ironlake_fdi_link_train(struct drm_crtc *crtc)

{
@@ -1767,27 +1798,6 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc) 


	DRM_DEBUG_KMS("FDI train done\n");



	/* enable normal train */

	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~FDI_LINK_TRAIN_NONE;

	temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;

	I915_WRITE(reg, temp);



	reg = FDI_RX_CTL(pipe);

	temp = I915_READ(reg);

	if (HAS_PCH_CPT(dev)) {

		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

		temp |= FDI_LINK_TRAIN_NORMAL_CPT;

	} else {

		temp &= ~FDI_LINK_TRAIN_NONE;

		temp |= FDI_LINK_TRAIN_NONE;

	}

	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);



	/* wait one idle pattern time */

	POSTING_READ(reg);

	udelay(1000);

}



static const int const snb_b_fdi_train_param [] = {
@@ -2090,6 +2100,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) 
	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));

	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));



	intel_fdi_normal_train(crtc);



	/* For PCH DP, enable TRANS_DP_CTL */

	if (HAS_PCH_CPT(dev) &&

	    intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {