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Commit 5d57c31e authored by Zhang Le's avatar Zhang Le Committed by Ralf Baechle
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MIPS: Loongson 2 needs no hazard barriers. 



Quoting from Loongson2FUserGuide.pdf:

5.22.1 Hazards
The processor detects most of the pipeline hazards in hardware, including
CP0 hazards and load hazards. No NOP instructions are required to correct
instruction sequences.

Signed-off-by: default avatarZhang Le <r0bertz@gentoo.org>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 6cec2a0a

arch/mips/include/asm/hazards.h

+3 −2
Original line number Diff line number Diff line
@@ -138,8 +138,9 @@ do { \ 
		__instruction_hazard();					\

} while (0)



#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \

      defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY)

#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \

      defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \

      defined(CONFIG_CPU_R5500)



/*

 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.