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Commit 5d1a566e authored by Tang Yuantian's avatar Tang Yuantian Committed by Scott Wood
Browse files

powerpc/mpc85xx: Update clock nodes in device tree 



The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240

Signed-off-by: default avatarTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: default avatarLi Yang <leoli@freescale.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent c7e64b9c

arch/powerpc/boot/dts/fsl/b4420si-post.dtsi

+36 −0
Original line number Diff line number Diff line
@@ -86,6 +86,42 @@ 


	clockgen: global-utilities@e1000 {

		compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";

		ranges = <0x0 0xe1000 0x1000>;

		#address-cells = <1>;

		#size-cells = <1>;



		sysclk: sysclk {

			#clock-cells = <0>;

			compatible = "fsl,qoriq-sysclk-2.0";

			clock-output-names = "sysclk";

		};



		pll0: pll0@800 {

			#clock-cells = <1>;

			reg = <0x800 0x4>;

			compatible = "fsl,qoriq-core-pll-2.0";

			clocks = <&sysclk>;

			clock-output-names = "pll0", "pll0-div2", "pll0-div4";

		};



		pll1: pll1@820 {

			#clock-cells = <1>;

			reg = <0x820 0x4>;

			compatible = "fsl,qoriq-core-pll-2.0";

			clocks = <&sysclk>;

			clock-output-names = "pll1", "pll1-div2", "pll1-div4";

		};



		mux0: mux0@0 {

			#clock-cells = <0>;

			reg = <0x0 0x4>;

			compatible = "fsl,qoriq-core-mux-2.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,

				<&pll1 0>, <&pll1 1>, <&pll1 2>;

			clock-names = "pll0", "pll0-div2", "pll0-div4",

				"pll1", "pll1-div2", "pll1-div4";

			clock-output-names = "cmux0";

		};

	};



	rcpm: global-utilities@e2000 {

arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -64,11 +64,13 @@ 
		cpu0: PowerPC,e6500@0 {

			device_type = "cpu";

			reg = <0 1>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

		};

		cpu1: PowerPC,e6500@2 {

			device_type = "cpu";

			reg = <2 3>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

		};

	};

arch/powerpc/boot/dts/fsl/b4860si-post.dtsi

+36 −0
Original line number Diff line number Diff line
@@ -130,6 +130,42 @@ 


	clockgen: global-utilities@e1000 {

		compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";

		ranges = <0x0 0xe1000 0x1000>;

		#address-cells = <1>;

		#size-cells = <1>;



		sysclk: sysclk {

			#clock-cells = <0>;

			compatible = "fsl,qoriq-sysclk-2.0";

			clock-output-names = "sysclk";

		};



		pll0: pll0@800 {

			#clock-cells = <1>;

			reg = <0x800 0x4>;

			compatible = "fsl,qoriq-core-pll-2.0";

			clocks = <&sysclk>;

			clock-output-names = "pll0", "pll0-div2", "pll0-div4";

		};



		pll1: pll1@820 {

			#clock-cells = <1>;

			reg = <0x820 0x4>;

			compatible = "fsl,qoriq-core-pll-2.0";

			clocks = <&sysclk>;

			clock-output-names = "pll1", "pll1-div2", "pll1-div4";

		};



		mux0: mux0@0 {

			#clock-cells = <0>;

			reg = <0x0 0x4>;

			compatible = "fsl,qoriq-core-mux-2.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,

				<&pll1 0>, <&pll1 1>, <&pll1 2>;

			clock-names = "pll0", "pll0-div2", "pll0-div4",

				"pll1", "pll1-div2", "pll1-div4";

			clock-output-names = "cmux0";

		};

	};



	rcpm: global-utilities@e2000 {

arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -64,21 +64,25 @@ 
		cpu0: PowerPC,e6500@0 {

			device_type = "cpu";

			reg = <0 1>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

		};

		cpu1: PowerPC,e6500@2 {

			device_type = "cpu";

			reg = <2 3>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

		};

		cpu2: PowerPC,e6500@4 {

			device_type = "cpu";

			reg = <4 5>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

		};

		cpu3: PowerPC,e6500@6 {

			device_type = "cpu";

			reg = <6 7>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

		};

	};

arch/powerpc/boot/dts/fsl/p2041si-post.dtsi

+60 −0
Original line number Diff line number Diff line
@@ -306,8 +306,68 @@ 


	clockgen: global-utilities@e1000 {

		compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";

		ranges = <0x0 0xe1000 0x1000>;

		reg = <0xe1000 0x1000>;

		clock-frequency = <0>;

		#address-cells = <1>;

		#size-cells = <1>;



		sysclk: sysclk {

			#clock-cells = <0>;

			compatible = "fsl,qoriq-sysclk-1.0";

			clock-output-names = "sysclk";

		};



		pll0: pll0@800 {

			#clock-cells = <1>;

			reg = <0x800 0x4>;

			compatible = "fsl,qoriq-core-pll-1.0";

			clocks = <&sysclk>;

			clock-output-names = "pll0", "pll0-div2";

		};



		pll1: pll1@820 {

			#clock-cells = <1>;

			reg = <0x820 0x4>;

			compatible = "fsl,qoriq-core-pll-1.0";

			clocks = <&sysclk>;

			clock-output-names = "pll1", "pll1-div2";

		};



		mux0: mux0@0 {

			#clock-cells = <0>;

			reg = <0x0 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux0";

		};



		mux1: mux1@20 {

			#clock-cells = <0>;

			reg = <0x20 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux1";

		};



		mux2: mux2@40 {

			#clock-cells = <0>;

			reg = <0x40 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

		};



		mux3: mux3@60 {

			#clock-cells = <0>;

			reg = <0x60 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux3";

		};

	};



	rcpm: global-utilities@e2000 {