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Commit 5d0f1b84 authored by Bjorn Helgaas's avatar Bjorn Helgaas
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PCI: qcom: Reorder to put v0 functions together, v1 functions together, etc 



Previously the v0, v1, and v2 functions were not grouped together in a
consistent order.  Reorder them to make them consistent.

Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 90d52d57

drivers/pci/dwc/pcie-qcom.c

+61 −61
Original line number Diff line number Diff line
@@ -152,26 +152,6 @@ static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg) 
	return dw_handle_msi_irq(pp);

}



static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)

{

	u32 val;



	/* enable link training */

	val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);

	val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;

	writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);

}



static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie)

{

	u32 val;



	/* enable link training */

	val = readl(pcie->parf + PCIE20_PARF_LTSSM);

	val |= BIT(8);

	writel(val, pcie->parf + PCIE20_PARF_LTSSM);

}



static int qcom_pcie_establish_link(struct qcom_pcie *pcie)

{

	struct dw_pcie *pci = pcie->pci;
@@ -186,6 +166,16 @@ static int qcom_pcie_establish_link(struct qcom_pcie *pcie) 
	return dw_pcie_wait_for_link(pci);

}



static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)

{

	u32 val;



	/* enable link training */

	val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);

	val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;

	writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);

}



static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
@@ -236,36 +226,6 @@ static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie) 
	return PTR_ERR_OR_ZERO(res->phy_reset);

}



static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v1 *res = &pcie->res.v1;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;



	res->vdda = devm_regulator_get(dev, "vdda");

	if (IS_ERR(res->vdda))

		return PTR_ERR(res->vdda);



	res->iface = devm_clk_get(dev, "iface");

	if (IS_ERR(res->iface))

		return PTR_ERR(res->iface);



	res->aux = devm_clk_get(dev, "aux");

	if (IS_ERR(res->aux))

		return PTR_ERR(res->aux);



	res->master_bus = devm_clk_get(dev, "master_bus");

	if (IS_ERR(res->master_bus))

		return PTR_ERR(res->master_bus);



	res->slave_bus = devm_clk_get(dev, "slave_bus");

	if (IS_ERR(res->slave_bus))

		return PTR_ERR(res->slave_bus);



	res->core = devm_reset_control_get(dev, "core");

	return PTR_ERR_OR_ZERO(res->core);

}



static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
@@ -394,6 +354,36 @@ static int qcom_pcie_init_v0(struct qcom_pcie *pcie) 
	return ret;

}



static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v1 *res = &pcie->res.v1;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;



	res->vdda = devm_regulator_get(dev, "vdda");

	if (IS_ERR(res->vdda))

		return PTR_ERR(res->vdda);



	res->iface = devm_clk_get(dev, "iface");

	if (IS_ERR(res->iface))

		return PTR_ERR(res->iface);



	res->aux = devm_clk_get(dev, "aux");

	if (IS_ERR(res->aux))

		return PTR_ERR(res->aux);



	res->master_bus = devm_clk_get(dev, "master_bus");

	if (IS_ERR(res->master_bus))

		return PTR_ERR(res->master_bus);



	res->slave_bus = devm_clk_get(dev, "slave_bus");

	if (IS_ERR(res->slave_bus))

		return PTR_ERR(res->slave_bus);



	res->core = devm_reset_control_get(dev, "core");

	return PTR_ERR_OR_ZERO(res->core);

}



static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
@@ -474,6 +464,16 @@ static int qcom_pcie_init_v1(struct qcom_pcie *pcie) 
	return ret;

}



static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie)

{

	u32 val;



	/* enable link training */

	val = readl(pcie->parf + PCIE20_PARF_LTSSM);

	val |= BIT(8);

	writel(val, pcie->parf + PCIE20_PARF_LTSSM);

}



static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
@@ -500,6 +500,17 @@ static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie) 
	return PTR_ERR_OR_ZERO(res->pipe_clk);

}



static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;



	clk_disable_unprepare(res->pipe_clk);

	clk_disable_unprepare(res->slave_clk);

	clk_disable_unprepare(res->master_clk);

	clk_disable_unprepare(res->cfg_clk);

	clk_disable_unprepare(res->aux_clk);

}



static int qcom_pcie_init_v2(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
@@ -867,17 +878,6 @@ static int qcom_pcie_link_up(struct dw_pcie *pci) 
	return !!(val & PCI_EXP_LNKSTA_DLLLA);

}



static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;



	clk_disable_unprepare(res->pipe_clk);

	clk_disable_unprepare(res->slave_clk);

	clk_disable_unprepare(res->master_clk);

	clk_disable_unprepare(res->cfg_clk);

	clk_disable_unprepare(res->aux_clk);

}



static void qcom_pcie_host_init(struct pcie_port *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);