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Commit 5cf161ce authored by David Collins's avatar David Collins
Browse files

clk: qcom: npucc-kona: correct ARES clock reset bit specifications 



The bit values specified for clock resets should be bit indices
not bit masks.  Correct this for ARES clock resets.

Change-Id: I49e250b95008524a6ae6db40dabc13c53b6bf84c
Signed-off-by: default avatarDavid Collins <collinsd@codeaurora.org>
parent 1dc55b85

drivers/clk/qcom/npucc-kona.c

+3 −3
Original line number Diff line number Diff line
@@ -1086,10 +1086,10 @@ static const struct qcom_reset_map npu_cc_kona_resets[] = { 
	[NPU_CC_CAL_HM0_BCR] = { 0x10f0 },

	[NPU_CC_CAL_HM1_BCR] = { 0x1130 },

	[NPU_CC_CORE_BCR] = { 0x1000 },

	[NPU_CC_DPM_TEMP_CLK_ARES] = { 0x10c4, BIT(2) },

	[NPU_CC_DPM_TEMP_CLK_ARES] = { 0x10c4, 2 },

	[NPU_CC_DSP_BCR] = { 0x1200 },

	[NPU_CC_LLM_CURR_CLK_ARES] = { 0x10d4, BIT(2) },

	[NPU_CC_LLM_TEMP_CLK_ARES] = { 0x10c8, BIT(2) },

	[NPU_CC_LLM_CURR_CLK_ARES] = { 0x10d4, 2 },

	[NPU_CC_LLM_TEMP_CLK_ARES] = { 0x10c8, 2 },

};



static const struct regmap_config npu_cc_kona_regmap_config = {