drm/amd/display: Decouple aux from i2c (5c6ac711) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c

+10 −12

Original line number	Original line	Diff line number	Diff line
	@@ -33,10 +33,8 @@
	#include "include/vector.h"		#include "include/vector.h"
	#include "core_types.h"		#include "core_types.h"
	#include "dc_link_ddc.h"		#include "dc_link_ddc.h"
	#include "i2caux/engine.h"		#include "engine.h"
	#include "i2caux/i2c_engine.h"		#include "aux_engine.h"
	#include "i2caux/aux_engine.h"
	#include "i2caux/i2caux.h"

	#define AUX_POWER_UP_WA_DELAY 500		#define AUX_POWER_UP_WA_DELAY 500
	#define I2C_OVER_AUX_DEFER_WA_DELAY 70		#define I2C_OVER_AUX_DEFER_WA_DELAY 70
	@@ -641,9 +639,9 @@ int dc_link_aux_transfer(struct ddc_service *ddc,
	enum aux_transaction_type type,		enum aux_transaction_type type,
	enum i2caux_transaction_action action)		enum i2caux_transaction_action action)
	{		{
	struct i2caux *i2caux = ddc->ctx->i2caux;
	struct ddc *ddc_pin = ddc->ddc_pin;		struct ddc *ddc_pin = ddc->ddc_pin;
	struct aux_engine *engine;		struct engine *engine;
			struct aux_engine *aux_engine;
	enum aux_channel_operation_result operation_result;		enum aux_channel_operation_result operation_result;
	struct aux_request_transaction_data aux_req;		struct aux_request_transaction_data aux_req;
	struct aux_reply_transaction_data aux_rep;		struct aux_reply_transaction_data aux_rep;
	@@ -654,7 +652,8 @@ int dc_link_aux_transfer(struct ddc_service *ddc,
	memset(&aux_req, 0, sizeof(aux_req));		memset(&aux_req, 0, sizeof(aux_req));
	memset(&aux_rep, 0, sizeof(aux_rep));		memset(&aux_rep, 0, sizeof(aux_rep));

	engine = i2caux->funcs->acquire_aux_engine(i2caux, ddc_pin);		engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
			aux_engine = engine->funcs->acquire(engine, ddc_pin);

	aux_req.type = type;		aux_req.type = type;
	aux_req.action = action;		aux_req.action = action;
	@@ -664,15 +663,15 @@ int dc_link_aux_transfer(struct ddc_service *ddc,
	aux_req.length = size;		aux_req.length = size;
	aux_req.data = buffer;		aux_req.data = buffer;

	engine->funcs->submit_channel_request(engine, &aux_req);		aux_engine->funcs->submit_channel_request(aux_engine, &aux_req);
	operation_result = engine->funcs->get_channel_status(engine, &returned_bytes);		operation_result = aux_engine->funcs->get_channel_status(aux_engine, &returned_bytes);

	switch (operation_result) {		switch (operation_result) {
	case AUX_CHANNEL_OPERATION_SUCCEEDED:		case AUX_CHANNEL_OPERATION_SUCCEEDED:
	res = returned_bytes;		res = returned_bytes;

	if (res <= size && res >= 0)		if (res <= size && res >= 0)
	res = engine->funcs->read_channel_reply(engine, size,		res = aux_engine->funcs->read_channel_reply(aux_engine, size,
	buffer, reply,		buffer, reply,
	&status);		&status);

	@@ -686,8 +685,7 @@ int dc_link_aux_transfer(struct ddc_service *ddc,
	res = -1;		res = -1;
	break;		break;
	}		}
			aux_engine->base.funcs->release_engine(&aux_engine->base);
	i2caux->funcs->release_engine(i2caux, &engine->base);
	return res;		return res;
	}		}

drivers/gpu/drm/amd/display/dc/dce/Makefile

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -28,7 +28,7 @@

	DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \		DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
	dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \		dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \
	dce_clocks.o dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o		dce_clocks.o dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o dce_aux.o


	AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))		AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

0 → 100644

+942 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

0 → 100644

+111 −0

Original line number	Original line	Diff line number	Diff line
			/*
			* Copyright 2012-15 Advanced Micro Devices, Inc.
			*
			* Permission is hereby granted, free of charge, to any person obtaining a
			* copy of this software and associated documentation files (the "Software"),
			* to deal in the Software without restriction, including without limitation
			* the rights to use, copy, modify, merge, publish, distribute, sublicense,
			* and/or sell copies of the Software, and to permit persons to whom the
			* Software is furnished to do so, subject to the following conditions:
			*
			* The above copyright notice and this permission notice shall be included in
			* all copies or substantial portions of the Software.
			*
			* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
			* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
			* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
			* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
			* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
			* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
			* OTHER DEALINGS IN THE SOFTWARE.
			*
			* Authors: AMD
			*
			*/

			#ifndef __DAL_AUX_ENGINE_DCE110_H__
			#define __DAL_AUX_ENGINE_DCE110_H__
			#include "aux_engine.h"

			#define AUX_COMMON_REG_LIST(id)\
			SRI(AUX_CONTROL, DP_AUX, id), \
			SRI(AUX_ARB_CONTROL, DP_AUX, id), \
			SRI(AUX_SW_DATA, DP_AUX, id), \
			SRI(AUX_SW_CONTROL, DP_AUX, id), \
			SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
			SRI(AUX_SW_STATUS, DP_AUX, id), \
			SR(AUXN_IMPCAL), \
			SR(AUXP_IMPCAL)

			struct dce110_aux_registers {
			uint32_t AUX_CONTROL;
			uint32_t AUX_ARB_CONTROL;
			uint32_t AUX_SW_DATA;
			uint32_t AUX_SW_CONTROL;
			uint32_t AUX_INTERRUPT_CONTROL;
			uint32_t AUX_SW_STATUS;
			uint32_t AUXN_IMPCAL;
			uint32_t AUXP_IMPCAL;

			uint32_t AUX_RESET_MASK;
			};

			enum { /* This is the timeout as defined in DP 1.2a,
			* 2.3.4 "Detailed uPacket TX AUX CH State Description".
			*/
			AUX_TIMEOUT_PERIOD = 400,

			/* Ideally, the SW timeout should be just above 550usec
			* which is programmed in HW.
			* But the SW timeout of 600usec is not reliable,
			* because on some systems, delay_in_microseconds()
			* returns faster than it should.
			* EPR #379763: by trial-and-error on different systems,
			* 700usec is the minimum reliable SW timeout for polling
			* the AUX_SW_STATUS.AUX_SW_DONE bit.
			* This timeout expires only when there is
			* AUX Error or AUX Timeout conditions - not during normal operation.
			* During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set
			* at most within ~240usec. That means,
			* increasing this timeout will not affect normal operation,
			* and we'll timeout after
			* SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 1600usec.
			* This timeout is especially important for
			* resume from S3 and CTS.
			*/
			SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4
			};
			struct aux_engine_dce110 {
			struct aux_engine base;
			const struct dce110_aux_registers *regs;
			struct {
			uint32_t aux_control;
			uint32_t aux_arb_control;
			uint32_t aux_sw_data;
			uint32_t aux_sw_control;
			uint32_t aux_interrupt_control;
			uint32_t aux_sw_status;
			} addr;
			uint32_t timeout_period;
			};

			struct aux_engine_dce110_init_data {
			uint32_t engine_id;
			uint32_t timeout_period;
			struct dc_context *ctx;
			const struct dce110_aux_registers *regs;
			};

			struct aux_engine *dce110_aux_engine_construct(
			struct aux_engine_dce110 *aux_engine110,
			struct dc_context *ctx,
			uint32_t inst,
			uint32_t timeout_period,
			const struct dce110_aux_registers *regs);

			void dce110_engine_destroy(struct engine **engine);

			bool dce110_aux_engine_acquire(
			struct engine *aux_engine,
			struct ddc *ddc);
			#endif

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

+42 −0

Original line number	Original line	Diff line number	Diff line
	@@ -52,6 +52,7 @@
	#include "dce/dce_10_0_sh_mask.h"		#include "dce/dce_10_0_sh_mask.h"

	#include "dce/dce_dmcu.h"		#include "dce/dce_dmcu.h"
			#include "dce/dce_aux.h"
	#include "dce/dce_abm.h"		#include "dce/dce_abm.h"

	#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT		#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
	@@ -279,7 +280,20 @@ static const struct dce_opp_shift opp_shift = {
	static const struct dce_opp_mask opp_mask = {		static const struct dce_opp_mask opp_mask = {
	OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)		OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
	};		};
			#define aux_engine_regs(id)\
			[id] = {\
			AUX_COMMON_REG_LIST(id), \
			.AUX_RESET_MASK = 0 \
			}

			static const struct dce110_aux_registers aux_engine_regs[] = {
			aux_engine_regs(0),
			aux_engine_regs(1),
			aux_engine_regs(2),
			aux_engine_regs(3),
			aux_engine_regs(4),
			aux_engine_regs(5)
			};

	#define audio_regs(id)\		#define audio_regs(id)\
	[id] = {\		[id] = {\
	@@ -572,6 +586,23 @@ struct output_pixel_processor *dce100_opp_create(
	return &opp->base;		return &opp->base;
	}		}

			struct engine *dce100_aux_engine_create(
			struct dc_context *ctx,
			uint32_t inst)
			{
			struct aux_engine_dce110 *aux_engine =
			kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);

			if (!aux_engine)
			return NULL;

			dce110_aux_engine_construct(aux_engine, ctx, inst,
			SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
			&aux_engine_regs[inst]);

			return &aux_engine->base.base;
			}

	struct clock_source *dce100_clock_source_create(		struct clock_source *dce100_clock_source_create(
	struct dc_context *ctx,		struct dc_context *ctx,
	struct dc_bios *bios,		struct dc_bios *bios,
	@@ -624,6 +655,10 @@ static void destruct(struct dce110_resource_pool *pool)
	kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));		kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
	pool->base.timing_generators[i] = NULL;		pool->base.timing_generators[i] = NULL;
	}		}

			if (pool->base.engines[i] != NULL)
			dce110_engine_destroy(&pool->base.engines[i]);

	}		}

	for (i = 0; i < pool->base.stream_enc_count; i++) {		for (i = 0; i < pool->base.stream_enc_count; i++) {
	@@ -928,6 +963,13 @@ static bool construct(
	"DC: failed to create output pixel processor!\n");		"DC: failed to create output pixel processor!\n");
	goto res_create_fail;		goto res_create_fail;
	}		}
			pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
			if (pool->base.engines[i] == NULL) {
			BREAK_TO_DEBUGGER();
			dm_error(
			"DC:failed to create aux engine!!\n");
			goto res_create_fail;
			}
	}		}

	dc->caps.max_planes = pool->base.pipe_count;		dc->caps.max_planes = pool->base.pipe_count;