Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5c0e0b45 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-4.17' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

A little bigger than normal since this is two weeks of fixes.
- Atom firmware table updates for vega12
- Fix fallout from huge page support
- Fix up smu7 power profile interface to be consistent with vega
- Misc other fixes

* 'drm-fixes-4.17' of git://people.freedesktop.org/~agd5f/linux:
  drm/amd/pp: Refine the output of pp_power_profile_mode on VI
  drm/amdgpu: Switch to interruptable wait to recover from ring hang.
  drm/ttm: Use GFP_TRANSHUGE_LIGHT for allocating huge pages
  drm/amd/display: Use kvzalloc for potentially large allocations
  drm/amd/display: Don't return ddc result and read_bytes in same return value
  drm/amd/display: Add get_firmware_info_v3_2 for VG12
  drm/amd: Add BIOS smu_info v3_3 required struct def.
  drm/amd/display: Add VG12 ASIC IDs
parents 44ef02c2 639f7902

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

+4 −2
Original line number Diff line number Diff line
@@ -419,9 +419,11 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id) 


	if (other) {

		signed long r;

		r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);

		r = dma_fence_wait(other, true);

		if (r < 0) {

			if (r != -ERESTARTSYS)

				DRM_ERROR("Error (%ld) waiting for fence!\n", r);



			return r;

		}

	}

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

+12 −8
Original line number Diff line number Diff line
@@ -83,21 +83,22 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 
	enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ?

		I2C_MOT_TRUE : I2C_MOT_FALSE;

	enum ddc_result res;

	ssize_t read_bytes;

	uint32_t read_bytes = msg->size;



	if (WARN_ON(msg->size > 16))

		return -E2BIG;



	switch (msg->request & ~DP_AUX_I2C_MOT) {

	case DP_AUX_NATIVE_READ:

		read_bytes = dal_ddc_service_read_dpcd_data(

		res = dal_ddc_service_read_dpcd_data(

				TO_DM_AUX(aux)->ddc_service,

				false,

				I2C_MOT_UNDEF,

				msg->address,

				msg->buffer,

				msg->size);

		return read_bytes;

				msg->size,

				&read_bytes);

		break;

	case DP_AUX_NATIVE_WRITE:

		res = dal_ddc_service_write_dpcd_data(

				TO_DM_AUX(aux)->ddc_service,
@@ -108,14 +109,15 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 
				msg->size);

		break;

	case DP_AUX_I2C_READ:

		read_bytes = dal_ddc_service_read_dpcd_data(

		res = dal_ddc_service_read_dpcd_data(

				TO_DM_AUX(aux)->ddc_service,

				true,

				mot,

				msg->address,

				msg->buffer,

				msg->size);

		return read_bytes;

				msg->size,

				&read_bytes);

		break;

	case DP_AUX_I2C_WRITE:

		res = dal_ddc_service_write_dpcd_data(

				TO_DM_AUX(aux)->ddc_service,
@@ -137,7 +139,9 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 
		 r == DDC_RESULT_SUCESSFULL);

#endif



	return msg->size;

	if (res != DDC_RESULT_SUCESSFULL)

		return -EIO;

	return read_bytes;

}



static enum drm_connector_status

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

+85 −1
Original line number Diff line number Diff line
@@ -70,6 +70,10 @@ static enum bp_result get_firmware_info_v3_1( 
	struct bios_parser *bp,

	struct dc_firmware_info *info);



static enum bp_result get_firmware_info_v3_2(

	struct bios_parser *bp,

	struct dc_firmware_info *info);



static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,

		struct atom_display_object_path_v2 *object);
@@ -1321,9 +1325,11 @@ static enum bp_result bios_parser_get_firmware_info( 
		case 3:

			switch (revision.minor) {

			case 1:

			case 2:

				result = get_firmware_info_v3_1(bp, info);

				break;

			case 2:

				result = get_firmware_info_v3_2(bp, info);

				break;

			default:

				break;

			}
@@ -1383,6 +1389,84 @@ static enum bp_result get_firmware_info_v3_1( 
	return BP_RESULT_OK;

}



static enum bp_result get_firmware_info_v3_2(

	struct bios_parser *bp,

	struct dc_firmware_info *info)

{

	struct atom_firmware_info_v3_2 *firmware_info;

	struct atom_display_controller_info_v4_1 *dce_info = NULL;

	struct atom_common_table_header *header;

	struct atom_data_revision revision;

	struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;

	struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;



	if (!info)

		return BP_RESULT_BADINPUT;



	firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,

			DATA_TABLES(firmwareinfo));



	dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,

			DATA_TABLES(dce_info));



	if (!firmware_info || !dce_info)

		return BP_RESULT_BADBIOSTABLE;



	memset(info, 0, sizeof(*info));



	header = GET_IMAGE(struct atom_common_table_header,

					DATA_TABLES(smu_info));

	get_atom_data_table_revision(header, &revision);



	if (revision.minor == 2) {

		/* Vega12 */

		smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,

							DATA_TABLES(smu_info));



		if (!smu_info_v3_2)

			return BP_RESULT_BADBIOSTABLE;



		info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;

	} else if (revision.minor == 3) {

		/* Vega20 */

		smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,

							DATA_TABLES(smu_info));



		if (!smu_info_v3_3)

			return BP_RESULT_BADBIOSTABLE;



		info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;

	}



	 // We need to convert from 10KHz units into KHz units.

	info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;



	 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */

	info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;

	/* Hardcode frequency if BIOS gives no DCE Ref Clk */

	if (info->pll_info.crystal_frequency == 0) {

		if (revision.minor == 2)

			info->pll_info.crystal_frequency = 27000;

		else if (revision.minor == 3)

			info->pll_info.crystal_frequency = 100000;

	}

	/*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/

	info->dp_phy_ref_clk     = dce_info->dpphy_refclk_10khz * 10;

	info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;



	/* Get GPU PLL VCO Clock */

	if (bp->cmd_tbl.get_smu_clock_info != NULL) {

		if (revision.minor == 2)

			info->smu_gpu_pll_output_freq =

					bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;

		else if (revision.minor == 3)

			info->smu_gpu_pll_output_freq =

					bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;

	}



	return BP_RESULT_OK;

}



static enum bp_result bios_parser_get_encoder_cap_info(

	struct dc_bios *dcb,

	struct graphics_object_id object_id,

drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c

+7 −3
Original line number Diff line number Diff line
@@ -629,13 +629,14 @@ bool dal_ddc_service_query_ddc_data( 
	return ret;

}



ssize_t dal_ddc_service_read_dpcd_data(

enum ddc_result dal_ddc_service_read_dpcd_data(

	struct ddc_service *ddc,

	bool i2c,

	enum i2c_mot_mode mot,

	uint32_t address,

	uint8_t *data,

	uint32_t len)

	uint32_t len,

	uint32_t *read)

{

	struct aux_payload read_payload = {

		.i2c_over_aux = i2c,
@@ -652,6 +653,8 @@ ssize_t dal_ddc_service_read_dpcd_data( 
		.mot = mot

	};



	*read = 0;



	if (len > DEFAULT_AUX_MAX_DATA_SIZE) {

		BREAK_TO_DEBUGGER();

		return DDC_RESULT_FAILED_INVALID_OPERATION;
@@ -661,7 +664,8 @@ ssize_t dal_ddc_service_read_dpcd_data( 
		ddc->ctx->i2caux,

		ddc->ddc_pin,

		&command)) {

		return (ssize_t)command.payloads->length;

		*read = command.payloads->length;

		return DDC_RESULT_SUCESSFULL;

	}



	return DDC_RESULT_FAILED_OPERATION;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

+7 −7
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc) 
{

	struct dc *core_dc = dc;



	struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state),

	struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),

						      GFP_KERNEL);



	if (NULL == plane_state)
@@ -120,7 +120,7 @@ static void dc_plane_state_free(struct kref *kref) 
{

	struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);

	destruct(plane_state);

	kfree(plane_state);

	kvfree(plane_state);

}



void dc_plane_state_release(struct dc_plane_state *plane_state)
@@ -136,7 +136,7 @@ void dc_gamma_retain(struct dc_gamma *gamma) 
static void dc_gamma_free(struct kref *kref)

{

	struct dc_gamma *gamma = container_of(kref, struct dc_gamma, refcount);

	kfree(gamma);

	kvfree(gamma);

}



void dc_gamma_release(struct dc_gamma **gamma)
@@ -147,7 +147,7 @@ void dc_gamma_release(struct dc_gamma **gamma) 


struct dc_gamma *dc_create_gamma(void)

{

	struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL);

	struct dc_gamma *gamma = kvzalloc(sizeof(*gamma), GFP_KERNEL);



	if (gamma == NULL)

		goto alloc_fail;
@@ -167,7 +167,7 @@ void dc_transfer_func_retain(struct dc_transfer_func *tf) 
static void dc_transfer_func_free(struct kref *kref)

{

	struct dc_transfer_func *tf = container_of(kref, struct dc_transfer_func, refcount);

	kfree(tf);

	kvfree(tf);

}



void dc_transfer_func_release(struct dc_transfer_func *tf)
@@ -177,7 +177,7 @@ void dc_transfer_func_release(struct dc_transfer_func *tf) 


struct dc_transfer_func *dc_create_transfer_func(void)

{

	struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL);

	struct dc_transfer_func *tf = kvzalloc(sizeof(*tf), GFP_KERNEL);



	if (tf == NULL)

		goto alloc_fail;