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Commit 5bf5dbed authored by Matthieu CASTET's avatar Matthieu CASTET Committed by Greg Kroah-Hartman
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usb: chipidea: need to mask when writting endptflush and endptprime 



ENDPTFLUSH and ENDPTPRIME registers are set by software and clear
by hardware. There is a bit for each endpoint. When we are setting
a bit for an endpoint we should make sure we do not touch other
endpoint bit. There is a race condition if the hardware clear the
bit between the read and the write in hw_write.

Cc: stable <stable@vger.kernel.org> # 3.11+
Signed-off-by: default avatarPeter Chen <peter.chen@freescale.com>
Signed-off-by: default avatarMatthieu CASTET <matthieu.castet@parrot.com>
Tested-by: default avatarMichael Grzeschik <mgrzeschik@pengutronix.de>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0fd7a820

drivers/usb/chipidea/udc.c

+2 −2
Original line number Diff line number Diff line
@@ -105,7 +105,7 @@ static int hw_ep_flush(struct ci_hdrc *ci, int num, int dir) 


	do {

		/* flush any pending transfer */

		hw_write(ci, OP_ENDPTFLUSH, BIT(n), BIT(n));

		hw_write(ci, OP_ENDPTFLUSH, ~0, BIT(n));

		while (hw_read(ci, OP_ENDPTFLUSH, BIT(n)))

			cpu_relax();

	} while (hw_read(ci, OP_ENDPTSTAT, BIT(n)));
@@ -205,7 +205,7 @@ static int hw_ep_prime(struct ci_hdrc *ci, int num, int dir, int is_ctrl) 
	if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num)))

		return -EAGAIN;



	hw_write(ci, OP_ENDPTPRIME, BIT(n), BIT(n));

	hw_write(ci, OP_ENDPTPRIME, ~0, BIT(n));



	while (hw_read(ci, OP_ENDPTPRIME, BIT(n)))

		cpu_relax();