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Commit 5bcbe22c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 

Pull crypto update from Herbert Xu:
 "API:
   - Try to catch hash output overrun in testmgr
   - Introduce walksize attribute for batched walking
   - Make crypto_xor() and crypto_inc() alignment agnostic

  Algorithms:
   - Add time-invariant AES algorithm
   - Add standalone CBCMAC algorithm

  Drivers:
   - Add NEON acclerated chacha20 on ARM/ARM64
   - Expose AES-CTR as synchronous skcipher on ARM64
   - Add scalar AES implementation on ARM64
   - Improve scalar AES implementation on ARM
   - Improve NEON AES implementation on ARM/ARM64
   - Merge CRC32 and PMULL instruction based drivers on ARM64
   - Add NEON acclerated CBCMAC/CMAC/XCBC AES on ARM64
   - Add IPsec AUTHENC implementation in atmel
   - Add Support for Octeon-tx CPT Engine
   - Add Broadcom SPU driver
   - Add MediaTek driver"

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (142 commits)
  crypto: xts - Add ECB dependency
  crypto: cavium - switch to pci_alloc_irq_vectors
  crypto: cavium - switch to pci_alloc_irq_vectors
  crypto: cavium - remove dead MSI-X related define
  crypto: brcm - Avoid double free in ahash_finup()
  crypto: cavium - fix Kconfig dependencies
  crypto: cavium - cpt_bind_vq_to_grp could return an error code
  crypto: doc - fix typo
  hwrng: omap - update Kconfig help description
  crypto: ccm - drop unnecessary minimum 32-bit alignment
  crypto: ccm - honour alignmask of subordinate MAC cipher
  crypto: caam - fix state buffer DMA (un)mapping
  crypto: caam - abstract ahash request double buffering
  crypto: caam - fix error path for ctx_dma mapping failure
  crypto: caam - fix DMA API leaks for multiple setkey() calls
  crypto: caam - don't dma_map key for hash algorithms
  crypto: caam - use dma_map_sg() return code
  crypto: caam - replace sg_count() with sg_nents_for_len()
  crypto: caam - check sg_count() return value
  crypto: caam - fix HW S/G in ablkcipher_giv_edesc_alloc()
  ..
parents 1db934a5 12cb3a1c

Documentation/crypto/api-digest.rst

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@@ -14,7 +14,7 @@ Asynchronous Message Digest API 
   :doc: Asynchronous Message Digest API



.. kernel-doc:: include/crypto/hash.h

   :functions: crypto_alloc_ahash crypto_free_ahash crypto_ahash_init crypto_ahash_digestsize crypto_ahash_reqtfm crypto_ahash_reqsize crypto_ahash_setkey crypto_ahash_finup crypto_ahash_final crypto_ahash_digest crypto_ahash_export crypto_ahash_import

   :functions: crypto_alloc_ahash crypto_free_ahash crypto_ahash_init crypto_ahash_digestsize crypto_ahash_reqtfm crypto_ahash_reqsize crypto_ahash_statesize crypto_ahash_setkey crypto_ahash_finup crypto_ahash_final crypto_ahash_digest crypto_ahash_export crypto_ahash_import



Asynchronous Hash Request Handle

--------------------------------

Documentation/crypto/api-skcipher.rst

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@@ -59,4 +59,4 @@ Synchronous Block Cipher API - Deprecated 
   :doc: Synchronous Block Cipher API



.. kernel-doc:: include/linux/crypto.h

   :functions: crypto_alloc_blkcipher rypto_free_blkcipher crypto_has_blkcipher crypto_blkcipher_name crypto_blkcipher_ivsize crypto_blkcipher_blocksize crypto_blkcipher_setkey crypto_blkcipher_encrypt crypto_blkcipher_encrypt_iv crypto_blkcipher_decrypt crypto_blkcipher_decrypt_iv crypto_blkcipher_set_iv crypto_blkcipher_get_iv
 
   :functions: crypto_alloc_blkcipher crypto_free_blkcipher crypto_has_blkcipher crypto_blkcipher_name crypto_blkcipher_ivsize crypto_blkcipher_blocksize crypto_blkcipher_setkey crypto_blkcipher_encrypt crypto_blkcipher_encrypt_iv crypto_blkcipher_decrypt crypto_blkcipher_decrypt_iv crypto_blkcipher_set_iv crypto_blkcipher_get_iv

Documentation/devicetree/bindings/crypto/brcm,spu-crypto.txt

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The Broadcom Secure Processing Unit (SPU) hardware supports symmetric

cryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware

blocks.



Required properties:

- compatible: Should be one of the following:

  brcm,spum-crypto - for devices with SPU-M hardware

  brcm,spu2-crypto - for devices with SPU2 hardware

  brcm,spu2-v2-crypto - for devices with enhanced SPU2 hardware features like SHA3

  and Rabin Fingerprint support

  brcm,spum-nsp-crypto - for the Northstar Plus variant of the SPU-M hardware



- reg: Should contain SPU registers location and length.

- mboxes: The mailbox channel to be used to communicate with the SPU.

  Mailbox channels correspond to DMA rings on the device.



Example:

	crypto@612d0000 {

		compatible = "brcm,spum-crypto";

		reg = <0 0x612d0000 0 0x900>;

		mboxes = <&pdc0 0>;

	};

Documentation/devicetree/bindings/crypto/mediatek-crypto.txt

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MediaTek cryptographic accelerators



Required properties:

- compatible: Should be "mediatek,eip97-crypto"

- reg: Address and length of the register set for the device

- interrupts: Should contain the five crypto engines interrupts in numeric

	order. These are global system and four descriptor rings.

- clocks: the clock used by the core

- clock-names: the names of the clock listed in the clocks property. These are

	"ethif", "cryp"

- power-domains: Must contain a reference to the PM domain.





Example:

	crypto: crypto@1b240000 {

		compatible = "mediatek,eip97-crypto";

		reg = <0 0x1b240000 0 0x20000>;

		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,

			 <&ethsys CLK_ETHSYS_CRYPTO>;

		clock-names = "ethif","cryp";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;

	};

MAINTAINERS

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@@ -3031,6 +3031,13 @@ W: http://www.cavium.com 
S:     Supported

F:     drivers/net/ethernet/cavium/liquidio/



CAVIUM OCTEON-TX CRYPTO DRIVER

M:	George Cherian <george.cherian@cavium.com>

L:	linux-crypto@vger.kernel.org

W:	http://www.cavium.com

S:	Supported

F:	drivers/crypto/cavium/cpt/



CC2520 IEEE-802.15.4 RADIO DRIVER

M:	Varka Bhadram <varkabhadram@gmail.com>

L:	linux-wpan@vger.kernel.org