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Commit 5ba70372 authored by Santosh Shilimkar's avatar Santosh Shilimkar
Browse files

ARM: l2x0: Determine the cache size 



The cache size is needed for to optimise range based
maintainance operations

Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Acked-by: default avatarLinus Walleij <linus.walleij@stericsson.com>
parent 7db27e86

arch/arm/include/asm/hardware/cache-l2x0.h

+1 −0
Original line number Diff line number Diff line
@@ -55,6 +55,7 @@ 
#define L2X0_CACHE_ID_PART_MASK		(0xf << 6)

#define L2X0_CACHE_ID_PART_L210		(1 << 6)

#define L2X0_CACHE_ID_PART_L310		(3 << 6)

#define L2X0_AUX_CTRL_WAY_SIZE_MASK	(0x3 << 17)



#ifndef __ASSEMBLY__

extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);

arch/arm/mm/cache-l2x0.c

+11 −2
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
static void __iomem *l2x0_base;

static DEFINE_SPINLOCK(l2x0_lock);

static uint32_t l2x0_way_mask;	/* Bitmask of active ways */

static uint32_t l2x0_size;



static inline void cache_wait_way(void __iomem *reg, unsigned long mask)

{
@@ -242,6 +243,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 
{

	__u32 aux;

	__u32 cache_id;

	__u32 way_size = 0;

	int ways;

	const char *type;
@@ -275,6 +277,13 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 


	l2x0_way_mask = (1 << ways) - 1;



	/*

	 * L2 cache Size =  Way size * Number of ways

	 */

	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;

	way_size = 1 << (way_size + 3);

	l2x0_size = ways * way_size * SZ_1K;



	/*

	 * Check if l2x0 controller is already enabled.

	 * If you are booting from non-secure mode
@@ -300,6 +309,6 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 
	outer_cache.disable = l2x0_disable;



	printk(KERN_INFO "%s cache controller enabled\n", type);

	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",

			 ways, cache_id, aux);

	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",

			ways, cache_id, aux, l2x0_size);

}