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Commit 5b9cdd24 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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MIPS: ingenic: Initial JZ4780 support 



Support the Ingenic JZ4780 SoC using the existing code under
arch/mips/jz4740 now that it has been generalised sufficiently.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/10164/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 8838245d

arch/mips/boot/dts/ingenic/jz4780.dtsi

0 → 100644
+111 −0
Original line number Original line Diff line number Diff line 
#include <dt-bindings/clock/jz4780-cgu.h>



/ {

	#address-cells = <1>;

	#size-cells = <1>;

	compatible = "ingenic,jz4780";



	cpuintc: interrupt-controller {

		#address-cells = <0>;

		#interrupt-cells = <1>;

		interrupt-controller;

		compatible = "mti,cpu-interrupt-controller";

	};



	intc: interrupt-controller@10001000 {

		compatible = "ingenic,jz4780-intc";

		reg = <0x10001000 0x50>;



		interrupt-controller;

		#interrupt-cells = <1>;



		interrupt-parent = <&cpuintc>;

		interrupts = <2>;

	};



	ext: ext {

		compatible = "fixed-clock";

		#clock-cells = <0>;

	};



	rtc: rtc {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <32768>;

	};



	cgu: jz4780-cgu@10000000 {

		compatible = "ingenic,jz4780-cgu";

		reg = <0x10000000 0x100>;



		clocks = <&ext>, <&rtc>;

		clock-names = "ext", "rtc";



		#clock-cells = <1>;

	};



	uart0: serial@10030000 {

		compatible = "ingenic,jz4780-uart";

		reg = <0x10030000 0x100>;



		interrupt-parent = <&intc>;

		interrupts = <51>;



		clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;

		clock-names = "baud", "module";



		status = "disabled";

	};



	uart1: serial@10031000 {

		compatible = "ingenic,jz4780-uart";

		reg = <0x10031000 0x100>;



		interrupt-parent = <&intc>;

		interrupts = <50>;



		clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;

		clock-names = "baud", "module";



		status = "disabled";

	};



	uart2: serial@10032000 {

		compatible = "ingenic,jz4780-uart";

		reg = <0x10032000 0x100>;



		interrupt-parent = <&intc>;

		interrupts = <49>;



		clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;

		clock-names = "baud", "module";



		status = "disabled";

	};



	uart3: serial@10033000 {

		compatible = "ingenic,jz4780-uart";

		reg = <0x10033000 0x100>;



		interrupt-parent = <&intc>;

		interrupts = <48>;



		clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;

		clock-names = "baud", "module";



		status = "disabled";

	};



	uart4: serial@10034000 {

		compatible = "ingenic,jz4780-uart";

		reg = <0x10034000 0x100>;



		interrupt-parent = <&intc>;

		interrupts = <34>;



		clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;

		clock-names = "baud", "module";



		status = "disabled";

	};

};

arch/mips/include/asm/cpu-type.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -32,12 +32,12 @@ static inline int __pure __get_cpu_type(const int cpu_type) 
	case CPU_4KC:

	case CPU_4KC:

	case CPU_ALCHEMY:

	case CPU_ALCHEMY:

	case CPU_PR4450:

	case CPU_PR4450:

	case CPU_JZRISC:

#endif

#endif





#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \

#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \

    defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)

    defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)

	case CPU_4KEC:

	case CPU_4KEC:

	case CPU_JZRISC:

#endif

#endif





#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2

#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2

arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h

+0 −3
Original line number Original line Diff line number Diff line
@@ -12,8 +12,6 @@ 
#define cpu_has_3k_cache	0

#define cpu_has_3k_cache	0

#define cpu_has_4k_cache	1

#define cpu_has_4k_cache	1

#define cpu_has_tx39_cache	0

#define cpu_has_tx39_cache	0

#define cpu_has_fpu		0

#define cpu_has_32fpr	0

#define cpu_has_counter		0

#define cpu_has_counter		0

#define cpu_has_watch		1

#define cpu_has_watch		1

#define cpu_has_divec		1

#define cpu_has_divec		1
@@ -34,7 +32,6 @@ 
#define cpu_has_ic_fills_f_dc	0

#define cpu_has_ic_fills_f_dc	0

#define cpu_has_pindexed_dcache 0

#define cpu_has_pindexed_dcache 0

#define cpu_has_mips32r1	1

#define cpu_has_mips32r1	1

#define cpu_has_mips32r2	0

#define cpu_has_mips64r1	0

#define cpu_has_mips64r1	0

#define cpu_has_mips64r2	0

#define cpu_has_mips64r2	0

#define cpu_has_dsp		0

#define cpu_has_dsp		0

arch/mips/include/asm/mach-jz4740/irq.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -21,6 +21,8 @@ 




#ifdef CONFIG_MACH_JZ4740

#ifdef CONFIG_MACH_JZ4740

# define NR_INTC_IRQS	32

# define NR_INTC_IRQS	32

#else

# define NR_INTC_IRQS	64

#endif

#endif





/* 1st-level interrupts */

/* 1st-level interrupts */
@@ -48,6 +50,8 @@ 
#define JZ4740_IRQ_IPU		JZ4740_IRQ(29)

#define JZ4740_IRQ_IPU		JZ4740_IRQ(29)

#define JZ4740_IRQ_LCD		JZ4740_IRQ(30)

#define JZ4740_IRQ_LCD		JZ4740_IRQ(30)





#define JZ4780_IRQ_TCU2		JZ4740_IRQ(25)



/* 2nd-level interrupts */

/* 2nd-level interrupts */

#define JZ4740_IRQ_DMA(x)	(JZ4740_IRQ(NR_INTC_IRQS) + (x))

#define JZ4740_IRQ_DMA(x)	(JZ4740_IRQ(NR_INTC_IRQS) + (x))

arch/mips/jz4740/Kconfig

+6 −0
Original line number Original line Diff line number Diff line
@@ -12,3 +12,9 @@ endchoice 
config MACH_JZ4740

config MACH_JZ4740

	bool

	bool

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_MIPS32_R1



config MACH_JZ4780

	bool

	select MIPS_CPU_SCACHE

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_SUPPORTS_HIGHMEM