ARM: dts: qcom: Add A650 v2 device tree file for GPU

&soc {

	gpu_opp_table_v2: gpu-opp-table_v2 {

		compatible = "operating-points-v2";

		opp-490000000 {

			opp-hz = /bits/ 64 <490000000>;

			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;

		};

		opp-400000000 {

			opp-hz = /bits/ 64 <400000000>;

			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;

		};

		opp-305000000 {

			opp-hz = /bits/ 64 <305000000>;

			opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

		};

	};

};

&msm_gpu {

	qcom,chipid = <0x06050001>;

	/* GPU OPP data */

	operating-points-v2 = <&gpu_opp_table_v2>;

	/* Power levels */

	qcom,gpu-pwrlevels {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "qcom,gpu-pwrlevels";

		qcom,gpu-pwrlevel@0 {

			reg = <0>;

			qcom,gpu-freq = <490000000>;

			qcom,bus-freq-ddr7 = <10>;

			qcom,bus-min-ddr7 = <10>;

			qcom,bus-max-ddr7 = <10>;

			qcom,bus-freq-ddr8 = <9>;

			qcom,bus-min-ddr8 = <9>;

			qcom,bus-max-ddr8 = <9>;

		};

		qcom,gpu-pwrlevel@1 {

			reg = <1>;

			qcom,gpu-freq = <400000000>;

			qcom,bus-freq-ddr7 = <10>;

			qcom,bus-min-ddr7 = <8>;

			qcom,bus-max-ddr7 = <10>;

			qcom,bus-freq-ddr8 = <9>;

			qcom,bus-min-ddr8 = <8>;

			qcom,bus-max-ddr8 = <9>;

		};

		qcom,gpu-pwrlevel@2 {

			reg = <2>;

			qcom,gpu-freq = <305000000>;

			qcom,bus-freq-ddr7 = <3>;

			qcom,bus-min-ddr7 = <2>;

			qcom,bus-max-ddr7 = <10>;

			qcom,bus-freq-ddr8 = <3>;

			qcom,bus-min-ddr8 = <2>;

			qcom,bus-max-ddr8 = <9>;

		};

		qcom,gpu-pwrlevel@3 {

			reg = <3>;

			qcom,gpu-freq = <0>;

			qcom,bus-freq = <0>;

			qcom,bus-min = <0>;

			qcom,bus-max = <0>;

		};

	};

};

	qcom,spss-test-firmware-name = "spss2t";	/* 8 chars max */

	qcom,spss-prod-firmware-name = "spss2p";	/* 8 chars max */

};

#include "kona-v2-gpu.dtsi"