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Commit 5ae89ee0 authored by Steven Miao's avatar Steven Miao
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bfin cache: dcplb map: add 16M dcplb map for BF60x 



use 16M data cplb map on BF60x to avoid too much dcplb miss overhead
cleanup cplb info

Signed-off-by: default avatarSteven Miao <realmz6@gmail.com>
parent 5b083091

arch/blackfin/include/asm/def_LPBlackfin.h

+2 −0
Original line number Diff line number Diff line
@@ -622,10 +622,12 @@ do { \ 
#define PAGE_SIZE_4KB      0x00010000	/* 4 KB page size */

#define PAGE_SIZE_1MB      0x00020000	/* 1 MB page size */

#define PAGE_SIZE_4MB      0x00030000	/* 4 MB page size */

#ifdef CONFIG_BF60x

#define PAGE_SIZE_16KB     0x00040000	/* 16 KB page size */

#define PAGE_SIZE_64KB     0x00050000	/* 64 KB page size */

#define PAGE_SIZE_16MB     0x00060000	/* 16 MB page size */

#define PAGE_SIZE_64MB     0x00070000	/* 64 MB page size */

#endif

#define CPLB_L1SRAM        0x00000020	/* 0=SRAM mapped in L1, 0=SRAM not

					 * mapped to L1

					 */

arch/blackfin/kernel/cplb-nompu/cplbinit.c

+13 −3
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) 
{

	int i_d, i_i;

	unsigned long addr;

	unsigned long cplb_pageflags, cplb_pagesize;



	struct cplb_entry *d_tbl = dcplb_tbl[cpu];

	struct cplb_entry *i_tbl = icplb_tbl[cpu];
@@ -49,11 +50,20 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) 
	/* Cover kernel memory with 4M pages.  */

	addr = 0;



	for (; addr < memory_start; addr += 4 * 1024 * 1024) {

#ifdef PAGE_SIZE_16MB

	cplb_pageflags = PAGE_SIZE_16MB;

	cplb_pagesize = SIZE_16M;

#else

	cplb_pageflags = PAGE_SIZE_4MB;

	cplb_pagesize = SIZE_4M;

#endif





	for (; addr < memory_start; addr += cplb_pagesize) {

		d_tbl[i_d].addr = addr;

		d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;

		d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags;

		i_tbl[i_i].addr = addr;

		i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;

		i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags;

	}



#ifdef CONFIG_ROMKERNEL

arch/blackfin/kernel/cplb-nompu/cplbmgr.c

+23 −4
Original line number Diff line number Diff line
@@ -145,7 +145,7 @@ MGR_ATTR static int dcplb_miss(int cpu) 
	unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();

	int status = bfin_read_DCPLB_STATUS();

	int idx;

	unsigned long d_data, base, addr1, eaddr;

	unsigned long d_data, base, addr1, eaddr, cplb_pagesize, cplb_pageflags;



	nr_dcplb_miss[cpu]++;

	if (unlikely(status & FAULT_USERSUPV))
@@ -167,18 +167,37 @@ MGR_ATTR static int dcplb_miss(int cpu) 
	if (unlikely(d_data == 0))

		return CPLB_NO_ADDR_MATCH;



	addr1 = addr & ~(SIZE_4M - 1);

	addr &= ~(SIZE_1M - 1);

	d_data |= PAGE_SIZE_1MB;

	if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {



	/* BF60x support large than 4M CPLB page size */

#ifdef PAGE_SIZE_16MB

	cplb_pageflags = PAGE_SIZE_16MB;

	cplb_pagesize = SIZE_16M;

#else

	cplb_pageflags = PAGE_SIZE_4MB;

	cplb_pagesize = SIZE_4M;

#endif



find_pagesize:

	addr1 = addr & ~(cplb_pagesize - 1);

	if (addr1 >= base && (addr1 + cplb_pagesize) <= eaddr) {

		/*

		 * This works because

		 * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.

		 */

		d_data |= PAGE_SIZE_4MB;

		d_data |= cplb_pageflags;

		addr = addr1;

		goto found_pagesize;

	} else {

		if (cplb_pagesize > SIZE_4M) {

			cplb_pageflags = PAGE_SIZE_4MB;

			cplb_pagesize = SIZE_4M;

			goto find_pagesize;

		}

	}



found_pagesize:

#ifdef CONFIG_BF60x

	if ((addr >= ASYNC_BANK0_BASE)

		&& (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))

arch/blackfin/kernel/cplbinfo.c

+7 −2
Original line number Diff line number Diff line
@@ -17,8 +17,13 @@ 
#include <asm/cplbinit.h>

#include <asm/blackfin.h>



static char const page_strtbl[][3] = { "1K", "4K", "1M", "4M" };

#define page(flags)    (((flags) & 0x30000) >> 16)

static char const page_strtbl[][4] = {

	"1K", "4K", "1M", "4M",

#ifdef CONFIG_BF60x

	"16K", "64K", "16M", "64M",

#endif

};

#define page(flags)    (((flags) & 0x70000) >> 16)

#define strpage(flags) page_strtbl[page(flags)]



struct cplbinfo_data {